bin_count_8bit.dly

第一章_Bin_count_8bit.rar

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Wed Oct 08 16:02:19 2003

File: bin_count_8bit.dly

 The 20 Worst Net Delays are:
-------------------------------
| Max Delay (ns)  | Netname   |
-------------------------------
   7.074            reset_ibuf
   4.350            divider<23>
   2.488            counter<7>
   2.237            counter<5>
   2.232            counter<4>
   1.973            counter<1>
   1.913            counter<0>
   1.755            counter<3>
   1.240            counter<6>
   1.161            counter<2>
   0.915            divider<20>
   0.898            divider<12>
   0.898            divider<10>
   0.898            divider<8>
   0.898            divider<22>
   0.898            divider<6>
   0.898            divider<18>
   0.898            divider<4>
   0.898            divider<16>
   0.898            divider<14>
---------------------------------

-------------------------------------------------------------------------------
                               Net Delays
-------------------------------------------------------------------------------

GLOBAL_LOGIC0
   PWR_GND_0.Y
         0.626  divider<1>.G1

GLOBAL_LOGIC0_0
   PWR_GND_1.Y
         0.626  counter<0>.G1

GLOBAL_LOGIC1
   PWR_VCC_0.X
         0.456  divider<1>.F1

GLOBAL_LOGIC1_0
   PWR_VCC_1.X
         0.456  counter<0>.F1

clk_bufgp
   clk_bufgp/BUFG.OUT
         0.755  divider<1>.CLK
         0.755  divider<3>.CLK
         0.755  divider<5>.CLK
         0.755  divider<7>.CLK
         0.755  divider<9>.CLK
         0.755  divider<11>.CLK
         0.755  divider<13>.CLK
         0.755  divider<15>.CLK
         0.755  divider<17>.CLK
         0.755  divider<19>.CLK
         0.755  divider<21>.CLK
         0.755  divider<23>.CLK

clk_bufgp/IBUFG
   clk.GCLKOUT
         0.007  clk_bufgp/BUFG.IN

counter<0>
   counter<0>.XQ
         1.913  bin_out<0>.O
         1.061  counter<0>.F2

counter<1>
   counter<0>.YQ
         1.973  bin_out<1>.O
         0.994  counter<0>.G3

counter<2>
   counter<2>.XQ
         1.161  bin_out<2>.O
         1.153  counter<2>.F1

counter<3>
   counter<2>.YQ
         1.755  bin_out<3>.O
         0.957  counter<2>.G4

counter<4>
   counter<4>.XQ
         2.232  bin_out<4>.O
         1.061  counter<4>.F2

counter<5>
   counter<4>.YQ
         2.237  bin_out<5>.O
         1.189  counter<4>.G1

counter<6>
   counter<6>.XQ
         1.240  bin_out<6>.O
         1.061  counter<6>.F2

counter<7>
   counter<6>.YQ
         2.488  bin_out<7>.O
         0.957  counter<6>.G4

counter_madd__n0000_inst_cy_1
   counter<0>.COUT
         0.000  counter<2>.CIN

counter_madd__n0000_inst_cy_3
   counter<2>.COUT
         0.000  counter<4>.CIN

counter_madd__n0000_inst_cy_5
   counter<4>.COUT
         0.000  counter<6>.CIN

divider<10>
   divider<9>.YQ
         0.898  divider<9>.G4

divider<11>
   divider<11>.XQ
         0.869  divider<11>.F3

divider<12>
   divider<11>.YQ
         0.898  divider<11>.G4

divider<13>
   divider<13>.XQ
         0.869  divider<13>.F3

divider<14>
   divider<13>.YQ
         0.898  divider<13>.G4

divider<15>
   divider<15>.XQ
         0.869  divider<15>.F3

divider<16>
   divider<15>.YQ
         0.898  divider<15>.G4

divider<17>
   divider<17>.XQ
         0.869  divider<17>.F3

divider<18>
   divider<17>.YQ
         0.898  divider<17>.G4

divider<19>
   divider<19>.XQ
         0.885  divider<19>.F3

divider<1>
   divider<1>.XQ
         0.869  divider<1>.F3

divider<20>
   divider<19>.YQ
         0.915  divider<19>.G4

divider<21>
   divider<21>.XQ
         0.869  divider<21>.F3

divider<22>
   divider<21>.YQ
         0.898  divider<21>.G4

divider<23>
   divider<23>.XQ
         4.350  divider<23>.F1
         3.074  counter<0>.CLK
         2.960  counter<2>.CLK
         3.025  counter<4>.CLK
         2.780  counter<6>.CLK

divider<2>
   divider<1>.YQ
         0.898  divider<1>.G4

divider<3>
   divider<3>.XQ
         0.869  divider<3>.F3

divider<4>
   divider<3>.YQ
         0.898  divider<3>.G4

divider<5>
   divider<5>.XQ
         0.869  divider<5>.F3

divider<6>
   divider<5>.YQ
         0.898  divider<5>.G4

divider<7>
   divider<7>.XQ
         0.869  divider<7>.F3

divider<8>
   divider<7>.YQ
         0.898  divider<7>.G4

divider<9>
   divider<9>.XQ
         0.869  divider<9>.F3

divider_madd__n0000_inst_cy_11
   divider<3>.COUT
         0.000  divider<5>.CIN

divider_madd__n0000_inst_cy_13
   divider<5>.COUT
         0.000  divider<7>.CIN

divider_madd__n0000_inst_cy_15
   divider<7>.COUT
         0.000  divider<9>.CIN

divider_madd__n0000_inst_cy_17
   divider<9>.COUT
         0.000  divider<11>.CIN

divider_madd__n0000_inst_cy_19
   divider<11>.COUT
         0.000  divider<13>.CIN

divider_madd__n0000_inst_cy_21
   divider<13>.COUT
         0.000  divider<15>.CIN

divider_madd__n0000_inst_cy_23
   divider<15>.COUT
         0.000  divider<17>.CIN

divider_madd__n0000_inst_cy_25
   divider<17>.COUT
         0.000  divider<19>.CIN

divider_madd__n0000_inst_cy_27
   divider<19>.COUT
         0.000  divider<21>.CIN

divider_madd__n0000_inst_cy_29
   divider<21>.COUT
         0.000  divider<23>.CIN

divider_madd__n0000_inst_cy_9
   divider<1>.COUT
         0.000  divider<3>.CIN

reset_ibuf
   reset.I
         6.076  divider<1>.SR
         6.521  divider<3>.SR
         6.685  divider<5>.SR
         6.799  divider<7>.SR
         6.647  divider<9>.SR
         6.561  divider<11>.SR
         6.625  divider<13>.SR
         6.759  divider<15>.SR
         6.603  divider<17>.SR
         6.815  divider<19>.SR
         6.970  divider<21>.SR
         7.074  divider<23>.SR
         6.882  counter<0>.SR
         6.114  counter<2>.SR
         6.685  counter<4>.SR
         6.788  counter<6>.SR