📄 bin_count_8bit.twr
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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml bin_count_8bit
bin_count_8bit.ncd -o bin_count_8bit.twr bin_count_8bit.pcf
Design file: bin_count_8bit.ncd
Physical constraint file: bin_count_8bit.pcf
Device,speed: xc2s200,-5 (PRODUCTION 1.27 2003-06-19)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
================================================================================
Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK" 25 nS HIGH 50.000000 % ;
276 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.751ns.
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All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK | 5.751| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 276 paths, 0 nets, and 47 connections
Design statistics:
Minimum period: 5.751ns (Maximum frequency: 173.883MHz)
Analysis completed Sun Jan 04 22:14:53 2004
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Peak Memory Usage: 49 MB
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