bin_count_8bit.vhd

来自「第一章_Bin_count_8bit.rar」· VHDL 代码 · 共 54 行

--***********************************
--*      8 Bit Binary Counter 	 *
--*  Filename : BIN_COUNT_8BIT.VHD  *
--***********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BIN_COUNT_8BIT is
    Port ( CLK     : in std_logic;
           RESET   : in std_logic;
           BIN_OUT : out std_logic_vector(7 downto 0));
end BIN_COUNT_8BIT;

architecture Behavioral of BIN_COUNT_8BIT is
  signal COUNTER   : std_logic_vector(7 downto 0);
  signal DIVIDER   : std_logic_vector(23 downto 1);
  signal COUNT_CLK : std_logic;
begin

--***************************
--*  Time Base Generation   *
--***************************

  process (CLK,RESET)

    begin
      if RESET    = '0' then
	    DIVIDER <= "00000000000000000000000";
	 elsif CLK'event and CLK = '1' then
	    DIVIDER <= DIVIDER + 1;
	 end if;
  end process;
  COUNT_CLK <= DIVIDER(23);

--**************************
--*  8 Bit Binary Counter  *
--**************************
	 	  
  process (COUNT_CLK,RESET)

    begin 
      if RESET    = '0' then 
	    COUNTER <= "00000000";
	 elsif COUNT_CLK'event and COUNT_CLK = '1' then
	    COUNTER <= COUNTER + 1;
   	 end if;
  end process;	
  BIN_OUT <= not (COUNTER);

end Behavioral;