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Optimizing unit <bin_count_8bit> ...Mapping all equations...Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bin_count_8bit, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5 Number of Slices: 21 out of 2352 0% Number of Slice Flip Flops: 29 out of 4704 0% Number of 4 input LUTs: 38 out of 4704 0% Number of bonded IOBs: 9 out of 144 6% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 21 |divider_21:q | NONE | 8 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 6.082ns (Maximum Frequency: 164.420MHz) Minimum input arrival time before clock: 5.560ns Maximum output required time after clock: 9.992ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -quiet -dd c:\hardware\bin_count_8bit/_ngo -ucBIN_COUNT_8BIT.ucf -p xc2s200-pq208-5 bin_count_8bit.ngc bin_count_8bit.ngd Reading NGO file "C:/HARDWARE/BIN_COUNT_8BIT/bin_count_8bit.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "BIN_COUNT_8BIT.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "bin_count_8bit.ngd" ...Writing NGDBUILD log file "bin_count_8bit.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s200pq208-5".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary: Number of errors: 0 Number of warnings: 0 Number of Slices: 15 out of 2,352 1% Number of Slices containing unrelated logic: 0 out of 15 0% Number of Slice Flip Flops: 29 out of 4,704 1% Total Number 4 input LUTs: 17 out of 4,704 1% Number used as LUTs: 2 Number used as a route-thru: 15 Number of bonded IOBs: 9 out of 140 6% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 406Additional JTAG gate count for IOBs: 480Peak Memory Usage: 54 MBMapping completed.See MAP report file "bin_count_8bit_map.mrp" for details.Completed process "Map".Mapping Module bin_count_8bit . . .
MAP command line:
map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o bin_count_8bit_map.ncd bin_count_8bit.ngd bin_count_8bit.pcf
Mapping Module bin_count_8bit: DONE
Started process "Place & Route".Release 5.1.03i - Par F.26Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Constraints file: bin_count_8bit.pcfLoading device database for application par from file "bin_count_8bit_map.ncd". "bin_count_8bit" is an NCD, version 2.37, device xc2s200, package pq208,speed -5Loading device for application par from file 'v200.nph' in environmentC:/Xilinx.Device speed data version: PRODUCTION 1.26 2002-11-01.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 9 out of 140 6% Number of LOCed External IOBs 9 out of 9 100% Number of SLICEs 15 out of 2352 1% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): 2 (set by user)Placer effort level (-pl): 2 (set by user)Placer cost table entry (-t): 1Router effort level (-rl): 2 (set by user)Starting initial Timing Analysis. REAL time: 0 secs Finished initial Timing Analysis. REAL time: 2 secs Phase 1.1Phase 1.1 (Checksum:9896c0) REAL time: 3 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs Phase 3.8..Phase 3.8 (Checksum:98bf47) REAL time: 3 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 3 secs Phase 5.18Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs Writing design to file bin_count_8bit.ncd.Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 1 secs Starting Router REAL time: 3 secs Phase 1: 74 unrouted; REAL time: 3 secs Phase 2: 60 unrouted; REAL time: 3 secs Phase 3: 0 unrouted; (0) REAL time: 3 secs Phase 4: 0 unrouted; (0) REAL time: 3 secs Phase 5: 0 unrouted; (0) REAL time: 3 secs Finished Router REAL time: 3 secs Total REAL time to router completion: 3 secs Total CPU time to router completion: 2 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| clk_bufgp | Global | 11 | 0.000 | 0.750 |+----------------------------+----------+--------+------------+-------------+| divider<21> | Local | 5 | 0.090 | 3.601 |+----------------------------+----------+--------+------------+-------------+Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- TS_CLK = PERIOD TIMEGRP "CLK" 25 nS HI | 25.000ns | 5.818ns | 11 GH 50.000000 % | | | --------------------------------------------------------------------------------All constraints were met.All signals are completely routed.Total REAL time to par completion: 3 secs Total CPU time to par completion: 2 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.Writing design to file bin_count_8bit.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Loading device database for application trce.exe from file "bin_count_8bit.ncd". "bin_count_8bit" is an NCD, version 2.37, device xc2s200, package pq208,speed -5Loading device for application trce.exe from file 'v200.nph' in environmentC:/Xilinx.Analysis completed Thu Jun 05 15:27:46 2003--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module bin_count_8bit . . .
PAR command line: par -w -ol 2 -t 1 bin_count_8bit_map.ncd bin_count_8bit.ncd bin_count_8bit.pcf
PAR completed successfully
Started process "Generate Programming File".Release 5.1.03i - Bitgen F.26Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Loading device database for application Bitgen from file "bin_count_8bit.ncd". "bin_count_8bit" is an NCD, version 2.37, device xc2s200, package pq208,speed -5Loading device for application Bitgen from file 'v200.nph' in environmentC:/Xilinx.Opened constraints file bin_count_8bit.pcf.Thu Jun 05 15:27:48 2003Running DRC.DRC detected 0 errors and 0 warnings.Creating bit map...Saving bit stream in "bin_count_8bit.bit".Bitstream generation is complete.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -quiet -dd c:\hardware\bin_count_8bit/_ngo -ucBIN_COUNT_8BIT.ucf -p xc2s200-pq208-5 bin_count_8bit.ngc bin_count_8bit.ngd Reading NGO file "C:/HARDWARE/BIN_COUNT_8BIT/bin_count_8bit.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "BIN_COUNT_8BIT.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "bin_count_8bit.ngd" ...Writing NGDBUILD log file "bin_count_8bit.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s200pq208-5".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary: Number of errors: 0 Number of warnings: 0 Number of Slices: 15 out of 2,352 1% Number of Slices containing unrelated logic: 0 out of 15 0% Number of Slice Flip Flops: 29 out of 4,704 1% Total Number 4 input LUTs: 17 out of 4,704 1% Number used as LUTs: 2 Number used as a route-thru: 15 Number of bonded IOBs: 9 out of 140 6% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 406Additional JTAG gate count for IOBs: 480Peak Memory Usage: 54 MBMapping completed.See MAP report file "bin_count_8bit_map.mrp" for details.Completed process "Map".Mapping Module bin_count_8bit . . .
MAP command line:
map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o bin_count_8bit_map.ncd bin_count_8bit.ngd bin_count_8bit.pcf
Mapping Module bin_count_8bit: DONE
Started process "Place & Route".Release 5.1.03i - Par F.26Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Constraints file: bin_count_8bit.pcfLoading device database for application par from file "bin_count_8bit_map.ncd". "bin_count_8bit" is an NCD, version 2.37, device xc2s200, package pq208,speed -5Loading device for application par from file 'v200.nph' in environmentC:/Xilinx.Device speed data version: PRODUCTION 1.26 2002-11-01.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 9 out of 140 6% Number of LOCed External IOBs 9 out of 9 100% Number of SLICEs 15 out of 2352 1% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): 2 (set by user)Placer effort level (-pl): 2 (set by user)Placer cost table entry (-t): 1Router effort level (-rl): 2 (set by user)Starting initial Timing Analysis. REAL time: 0 secs Finished initial Timing Analysis. REAL time: 2 secs Phase 1.1Phase 1.1 (Checksum:9896c0) REAL time: 2 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs Phase 3.8..Phase 3.8 (Checksum:98bf47) REAL time: 2 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.18Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs Writing design to file bin_count_8bit.ncd.Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 1 secs ⌨️ 快捷键说明
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