bin_count_8bit.syr

第一章_Bin_count_8bit.rar

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: bin_count_8bit.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : bin_count_8bit.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : bin_count_8bit
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : bin_count_8bit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : bin_count_8bit.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/BIN_COUNT_8BIT is now defined in a different file: was C:/BOOK_128M/Bin_count_8bit/BIN_COUNT_8BIT.VHD, now is C:/DMATEK_BOOK/Bin_count_8bit/BIN_COUNT_8BIT.VHD
WARNING:HDLParsers:3215 - Unit work/BIN_COUNT_8BIT/BEHAVIORAL is now defined in a different file: was C:/BOOK_128M/Bin_count_8bit/BIN_COUNT_8BIT.VHD, now is C:/DMATEK_BOOK/Bin_count_8bit/BIN_COUNT_8BIT.VHD
Compiling vhdl file C:/DMATEK_BOOK/Bin_count_8bit/BIN_COUNT_8BIT.VHD in Library work.
Entity <BIN_COUNT_8BIT> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <bin_count_8bit> (Architecture <Behavioral>).
Entity <bin_count_8bit> analyzed. Unit <bin_count_8bit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <bin_count_8bit>.
    Related source file is C:/DMATEK_BOOK/Bin_count_8bit/BIN_COUNT_8BIT.VHD.
    Found 8-bit up counter for signal <COUNTER>.
    Found 23-bit up counter for signal <DIVIDER>.
    Summary:
	inferred   2 Counter(s).
Unit <bin_count_8bit> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
  23-bit up counter                : 1
  8-bit up counter                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <bin_count_8bit> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block bin_count_8bit, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : bin_count_8bit.ngr
Top Level Output File Name         : bin_count_8bit
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 10

Macro Statistics :
# Registers                        : 2
#      23-bit register             : 2
# Adders/Subtractors               : 2
#      23-bit adder                : 2

Cell Usage :
# BELS                             : 100
#      GND                         : 1
#      LUT1                        : 9
#      LUT1_D                      : 1
#      LUT1_L                      : 30
#      MUXCY                       : 29
#      VCC                         : 1
#      XORCY                       : 29
# FlipFlops/Latches                : 31
#      FDC                         : 31
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 9
#      IBUF                        : 1
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      22  out of   2352     0%  
 Number of Slice Flip Flops:            31  out of   4704     0%  
 Number of 4 input LUTs:                40  out of   4704     0%  
 Number of bonded IOBs:                  9  out of    144     6%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 23    |
DIVIDER_23:Q                       | NONE                   | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.182ns (Maximum Frequency: 161.760MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.992ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               6.182ns (Levels of Logic = 24)
  Source:            DIVIDER_1 (FF)
  Destination:       DIVIDER_23 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: DIVIDER_1 to DIVIDER_23
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.292   1.150  DIVIDER_1 (DIVIDER_1)
     LUT1_D:I0->LO         1   0.653   0.000  DIVIDER_Madd__n0000_inst_lut2_81 (N800)
     MUXCY:S->O            1   0.784   0.000  DIVIDER_Madd__n0000_inst_cy_8 (DIVIDER_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_9 (DIVIDER_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_10 (DIVIDER_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_11 (DIVIDER_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_12 (DIVIDER_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_13 (DIVIDER_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_14 (DIVIDER_Madd__n0000_inst_cy_14)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_15 (DIVIDER_Madd__n0000_inst_cy_15)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_16 (DIVIDER_Madd__n0000_inst_cy_16)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_17 (DIVIDER_Madd__n0000_inst_cy_17)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_18 (DIVIDER_Madd__n0000_inst_cy_18)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_19 (DIVIDER_Madd__n0000_inst_cy_19)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_20 (DIVIDER_Madd__n0000_inst_cy_20)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_21 (DIVIDER_Madd__n0000_inst_cy_21)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_22 (DIVIDER_Madd__n0000_inst_cy_22)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_23 (DIVIDER_Madd__n0000_inst_cy_23)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_24 (DIVIDER_Madd__n0000_inst_cy_24)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_25 (DIVIDER_Madd__n0000_inst_cy_25)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_26 (DIVIDER_Madd__n0000_inst_cy_26)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_27 (DIVIDER_Madd__n0000_inst_cy_27)
     MUXCY:CI->O           1   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_28 (DIVIDER_Madd__n0000_inst_cy_28)
     MUXCY:CI->O           0   0.050   0.000  DIVIDER_Madd__n0000_inst_cy_29 (DIVIDER_Madd__n0000_inst_cy_29)
     XORCY:CI->O           1   0.500   0.000  DIVIDER_Madd__n0000_inst_sum_30 (DIVIDER__n0000<22>)
     FDC:D                     0.753          DIVIDER_23
    ----------------------------------------
    Total                      6.182ns (5.032ns logic, 1.150ns route)
                                       (81.4% logic, 18.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DIVIDER_23:Q'
Delay:               5.622ns (Levels of Logic = 9)
  Source:            COUNTER_0 (FF)
  Destination:       COUNTER_7 (FF)
  Source Clock:      DIVIDER_23:Q rising
  Destination Clock: DIVIDER_23:Q rising

  Data Path: COUNTER_0 to COUNTER_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   1.292   1.340  COUNTER_0 (COUNTER_0)
     LUT1_L:I0->LO         2   0.653   0.000  COUNTER_Madd__n0000_inst_lut2_01 (COUNTER_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.784   0.000  COUNTER_Madd__n0000_inst_cy_0 (COUNTER_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  COUNTER_Madd__n0000_inst_cy_1 (COUNTER_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  COUNTER_Madd__n0000_inst_cy_2 (COUNTER_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.050   0.000  COUNTER_Madd__n0000_inst_cy_3 (COUNTER_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.050   0.000  COUNTER_Madd__n0000_inst_cy_4 (COUNTER_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.050   0.000  COUNTER_Madd__n0000_inst_cy_5 (COUNTER_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           0   0.050   0.000  COUNTER_Madd__n0000_inst_cy_6 (COUNTER_Madd__n0000_inst_cy_6)
     XORCY:CI->O           1   0.500   0.000  COUNTER_Madd__n0000_inst_sum_7 (COUNTER__n0000<7>)
     FDC:D                     0.753          COUNTER_7
    ----------------------------------------
    Total                      5.622ns (4.282ns logic, 1.340ns route)
                                       (76.2% logic, 23.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'DIVIDER_23:Q'
Offset:              9.992ns (Levels of Logic = 2)
  Source:            COUNTER_7 (FF)
  Destination:       BIN_OUT<7> (PAD)
  Source Clock:      DIVIDER_23:Q rising

  Data Path: COUNTER_7 to BIN_OUT<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   1.292   1.340  COUNTER_7 (COUNTER_7)
     LUT1:I0->O            1   0.653   1.150  BIN_OUT<7>1 (BIN_OUT_7_OBUF)
     OBUF:I->O                 5.557          BIN_OUT_7_OBUF (BIN_OUT<7>)
    ----------------------------------------
    Total                      9.992ns (7.502ns logic, 2.490ns route)
                                       (75.1% logic, 24.9% route)

=========================================================================
CPU : 2.04 / 2.66 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 59116 kilobytes