bin_count_8bit.par

第一章_Bin_count_8bit.rar

Constraints file: bin_count_8bit.pcf

Loading device database for application Par from file "bin_count_8bit_map.ncd".
   "bin_count_8bit" is an NCD, version 2.38, device xc2s200, package pq208,
speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-06-19.


Resolved that IOB <BIN_OUT<0>> must be placed at site P44.
Resolved that IOB <BIN_OUT<1>> must be placed at site P45.
Resolved that IOB <BIN_OUT<2>> must be placed at site P46.
Resolved that IOB <BIN_OUT<3>> must be placed at site P47.
Resolved that IOB <BIN_OUT<4>> must be placed at site P48.
Resolved that IOB <BIN_OUT<5>> must be placed at site P49.
Resolved that IOB <BIN_OUT<6>> must be placed at site P57.
Resolved that IOB <BIN_OUT<7>> must be placed at site P58.
Resolved that GCLKIOB <CLK> must be placed at site P80.
Resolved that IOB <RESET> must be placed at site P180.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             9 out of 140     6%
      Number of LOCed External IOBs    9 out of 9     100%

   Number of SLICEs                   16 out of 2352    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:9896c0) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98e46d) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file bin_count_8bit.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 90 unrouted;       REAL time: 0 secs 

Phase 2: 78 unrouted;       REAL time: 0 secs 

Phase 3: 1 unrouted;       REAL time: 0 secs 

Phase 4: 1 unrouted; (0)      REAL time: 2 secs 

Phase 5: 1 unrouted; (0)      REAL time: 2 secs 

Phase 6: 1 unrouted; (0)      REAL time: 2 secs 

Phase 7: 0 unrouted; (0)      REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |   12   |  0.000     |  0.751      |
+----------------------------+----------+--------+------------+-------------+
|       DIVIDER<23>          |   Local  |    5   |  0.543     |  3.269      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 262


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.082
   The MAXIMUM PIN DELAY IS:                               8.414
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.712

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00
   ---------   ---------   ---------   ---------   ---------   ---------
          66           8           2          10           4           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HI | 25.000ns   | 5.751ns    | 12   
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  58 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file bin_count_8bit.ncd.


PAR done.