watch_dog.v

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/*******************************************************************************
** Module               : watchdog    

** Project              : SPWM Signal generator IP core

*******************************************************************************

** File                 : watchdog.v      

** Author               : liangyi        <[e-mail]>

**                        qinghuahuang   <[e-mail]>

**                        yaozhangchen   <[e-mail]>

** Creation Date        : 05/01/03                                              

** Last update          : 07/05/03

** Version Number       : 0.1                                                 

** Simulators           : Cadence_LDV

** Synthesizers         : LeonardoSpectrum

*******************************************************************************

** Description          : The Watchdog Timer consists of a 16-bit progrmmable
                          counter,which is decremented at a sub-multiple of sys
                          -tem clock frequency.If the counter is allowed to reach 
                          its teminal condiion(time-out),then the PWM output are 
                          set to the off(low) state and the trip_out output asse
                          -rted low.  
                          if wte=1 watchdog is enable ,else watchdog is disable.
                           
*******************************************************************************/



module             watch_dog(SYSCLK,RESET,reset_in,WR,RD,wte,wd,overflow);
input              SYSCLK;            //global clock
input              RESET;
input              reset_in;          //global reset
input              WR;                //write strobe (read / write) 
input              RD;                //read strobe (data strobe)
input              wte;               //watchdog enable bit
input [15:0]       wd;                //watchdog counter word

output             overflow;          //overflow flag

reg                overflow;          //overflow flag register
reg                count_clk;         //count clock
reg                sign;

wire               rst;

reg[9:0]  counter;
reg [15:0]dog_counter;

always@(posedge SYSCLK)
       if(!RESET)
          begin
            if(RD) sign=1'b1;       //intel rd_/wd_ mode sign=1
            else   sign=1'b0;       //moto r/w_ mode sign=0
          end

assign rst=(sign) ? (reset_in & WR & RD) : (reset_in & (!RD));     //watchdog reset signal

always @(posedge SYSCLK )
       if(!rst)
           dog_counter<=16'h0000;
       else if(wte & count_clk)       //watchdog counter
           dog_counter<=dog_counter+1;
  
always @(posedge SYSCLK )
       if(!rst)
           overflow=1'b0;
       else if(wte & (dog_counter==wd))
           overflow=1'b1;                //watchdog overflow 

always@(posedge SYSCLK )
       if(!rst) begin
                  count_clk=1'b0;
                  counter=1'b0;
               end
       else if(wte)
          {count_clk,counter}=counter+1;  //watvhdog counter clock generator
          
endmodule