count.rpt

用PLC程序编写十字路口的交通灯

  _EQ021 =  en & !_LC6_C20
         # !en &  _LC2_C3 &  _LC6_C20
         # !en & !_LC4_C17 &  _LC6_C20;

-- Node name is '~582~1' 
-- Equation name is '~582~1', location is LC3_C2, type is buried.
-- synthesized logic cell 
_LC3_C2  = LCELL( _EQ022);
  _EQ022 =  _LC2_C2
         #  _LC2_C20
         #  _LC1_C5
         #  _LC3_C5;

-- Node name is ':582' 
-- Equation name is '_LC4_C2', type is buried 
!_LC4_C2 = _LC4_C2~NOT;
_LC4_C2~NOT = LCELL( _EQ023);
  _EQ023 = !_LC7_C1
         #  _LC8_C1
         #  _LC8_C2
         #  _LC3_C2;

-- Node name is '~597~1' 
-- Equation name is '~597~1', location is LC2_C17, type is buried.
-- synthesized logic cell 
_LC2_C17 = LCELL( _EQ024);
  _EQ024 =  _LC3_C20
         #  _LC5_C20
         #  _LC1_C3
         #  _LC6_C4;

-- Node name is ':597' 
-- Equation name is '_LC4_C17', type is buried 
!_LC4_C17 = _LC4_C17~NOT;
_LC4_C17~NOT = LCELL( _EQ025);
  _EQ025 =  _LC2_C17
         # !_LC6_C20
         #  _LC6_C17
         #  _LC1_C17;

-- Node name is ':792' 
-- Equation name is '_LC2_C3', type is buried 
_LC2_C3  = LCELL( _EQ026);
  _EQ026 = !s0 & !s1 &  s2;

-- Node name is ':802' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ027);
  _EQ027 =  s0 &  s1 & !s2;

-- Node name is ':822' 
-- Equation name is '_LC3_C12', type is buried 
!_LC3_C12 = _LC3_C12~NOT;
_LC3_C12~NOT = LCELL( _EQ028);
  _EQ028 = !s0
         #  s1
         #  s2;

-- Node name is ':832' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = LCELL( _EQ029);
  _EQ029 = !s0 & !s1 & !s2;

-- Node name is ':928' 
-- Equation name is '_LC2_C12', type is buried 
!_LC2_C12 = _LC2_C12~NOT;
_LC2_C12~NOT = LCELL( _EQ030);
  _EQ030 =  s1 &  s2
         # !s0 & !s1 & !s2
         #  s0 &  s2;

-- Node name is ':1312' 
-- Equation name is '_LC1_C2', type is buried 
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( _EQ031);
  _EQ031 =  _LC2_C2
         #  _LC8_C2
         #  _LC8_C1
         #  _LC7_C1;

-- Node name is ':1407' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _EQ032);
  _EQ032 =  _LC1_C5 &  _LC2_C20
         #  _LC2_C20 &  _LC3_C5
         #  _LC1_C2 & !_LC1_C5 & !_LC2_C20 & !_LC3_C5
         # !_LC1_C2 &  _LC2_C20;

-- Node name is ':1413' 
-- Equation name is '_LC6_C5', type is buried 
_LC6_C5  = LCELL( _EQ033);
  _EQ033 =  _LC1_C5 &  _LC3_C5
         #  _LC1_C2 & !_LC1_C5 & !_LC3_C5
         # !_LC1_C2 &  _LC1_C5;

-- Node name is ':1444' 
-- Equation name is '_LC6_C2', type is buried 
_LC6_C2  = LCELL( _EQ034);
  _EQ034 = !_LC1_C12 &  _LC2_C12 &  _LC4_C2
         # !_LC4_C2 &  _LC5_C2;

-- Node name is '~1445~1' 
-- Equation name is '~1445~1', location is LC5_C2, type is buried.
-- synthesized logic cell 
_LC5_C2  = LCELL( _EQ035);
  _EQ035 = !_LC1_C2 &  _LC8_C1 &  _LC8_C2
         # !_LC1_C2 &  _LC7_C1 &  _LC8_C2
         # !_LC1_C2 & !_LC7_C1 & !_LC8_C1 & !_LC8_C2;

-- Node name is ':1462' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ036);
  _EQ036 =  _LC1_C12 &  _LC4_C2
         #  _LC2_C3 &  _LC4_C2
         # !_LC4_C2 &  _LC7_C5;

-- Node name is ':1475' 
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = LCELL( _EQ037);
  _EQ037 = !_LC1_C2 &  _LC3_C5 & !_LC4_C2
         #  _LC1_C2 & !_LC3_C5 & !_LC4_C2;

-- Node name is ':1476' 
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = LCELL( _EQ038);
  _EQ038 = !_LC1_C12 &  _LC4_C2 &  _LC8_C5;

-- Node name is ':1502' 
-- Equation name is '_LC8_C17', type is buried 
!_LC8_C17 = _LC8_C17~NOT;
_LC8_C17~NOT = LCELL( _EQ039);
  _EQ039 =  _LC1_C17
         #  _LC3_C20
         #  _LC5_C20
         #  _LC6_C20;

-- Node name is ':1597' 
-- Equation name is '_LC5_C17', type is buried 
_LC5_C17 = LCELL( _EQ040);
  _EQ040 =  _LC1_C3 &  _LC6_C17
         #  _LC6_C4 &  _LC6_C17
         # !_LC1_C3 & !_LC6_C4 & !_LC6_C17 &  _LC8_C17
         #  _LC6_C17 & !_LC8_C17;

-- Node name is ':1603' 
-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = LCELL( _EQ041);
  _EQ041 =  _LC1_C3 &  _LC6_C4
         # !_LC1_C3 & !_LC6_C4 &  _LC8_C17
         #  _LC1_C3 & !_LC8_C17;

-- Node name is '~1635~1' 
-- Equation name is '~1635~1', location is LC1_C20, type is buried.
-- synthesized logic cell 
_LC1_C20 = LCELL( _EQ042);
  _EQ042 = !_LC4_C17 & !_LC8_C17;

-- Node name is ':1635' 
-- Equation name is '_LC7_C20', type is buried 
_LC7_C20 = LCELL( _EQ043);
  _EQ043 =  _LC3_C20 & !_LC4_C17 &  _LC4_C20 & !_LC8_C17
         # !_LC3_C20 & !_LC4_C17 & !_LC4_C20 & !_LC8_C17;

-- Node name is ':1636' 
-- Equation name is '_LC8_C20', type is buried 
_LC8_C20 = LCELL( _EQ044);
  _EQ044 =  _LC1_C12 &  _LC4_C17
         # !_LC2_C12 &  _LC4_C17;

-- Node name is ':1652' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = LCELL( _EQ045);
  _EQ045 =  _LC1_C12 &  _LC4_C17
         # !_LC4_C17 &  _LC5_C17;

-- Node name is ':1658' 
-- Equation name is '_LC7_C3', type is buried 
_LC7_C3  = LCELL( _EQ046);
  _EQ046 =  _LC1_C12 &  _LC4_C17
         #  _LC2_C3 &  _LC4_C17
         # !_LC4_C17 &  _LC5_C3;

-- Node name is ':1664' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = LCELL( _EQ047);
  _EQ047 = !_LC4_C17 &  _LC6_C4 & !_LC8_C17
         # !_LC4_C17 & !_LC6_C4 &  _LC8_C17
         #  _LC2_C4 &  _LC4_C17;

-- Node name is '~1666~1' 
-- Equation name is '~1666~1', location is LC2_C4, type is buried.
-- synthesized logic cell 
_LC2_C4  = LCELL( _EQ048);
  _EQ048 = !s0 &  s2;

-- Node name is '~1743~1' 
-- Equation name is '~1743~1', location is LC1_C1, type is buried.
-- synthesized logic cell 
_LC1_C1  = LCELL( _EQ049);
  _EQ049 = !_LC1_C2 &  _LC7_C1 &  _LC8_C1
         # !_LC1_C2 & !_LC7_C1 & !_LC8_C1;

-- Node name is ':1898' 
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = LCELL( _EQ050);
  _EQ050 =  s0 & !s1 &  s2;

-- Node name is ':1906' 
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = LCELL( _EQ051);
  _EQ051 =  s0 &  s1 &  s2;

-- Node name is ':1967' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = LCELL( _EQ052);
  _EQ052 =  s1 &  s2
         # !s0 & !s1 & !s2
         #  s0 &  s2;

-- Node name is ':2021' 
-- Equation name is '_LC8_C5', type is buried 
_LC8_C5  = LCELL( _EQ053);
  _EQ053 = !s0 & !s1 &  s2
         # !s0 &  s1 & !s2;

-- Node name is ':2073' 
-- Equation name is '_LC7_C4', type is buried 
!_LC7_C4 = _LC7_C4~NOT;
_LC7_C4~NOT = LCELL( _EQ054);
  _EQ054 =  s1 &  s2
         # !s0 & !s1 & !s2
         #  s0 &  s2;

-- Node name is ':2129' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ055);
  _EQ055 = !s0 & !s1 & !s2
         # !s0 &  s1 &  s2;



Project Information                                           c:\rgy\count.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,732K