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📄 light.rpt

📁 用PLC程序编写十字路口的交通灯
💻 RPT
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         #  _LC3_B7 &  _LC6_B6;

-- Node name is '~1058~1' 
-- Equation name is '~1058~1', location is LC3_B9, type is buried.
-- synthesized logic cell 
_LC3_B9  = LCELL( _EQ022);
  _EQ022 =  flag1
         # !flag2;

-- Node name is ':1058' 
-- Equation name is '_LC7_B7', type is buried 
_LC7_B7  = LCELL( _EQ023);
  _EQ023 =  flag1 &  _LC3_B7
         # !flag2 &  _LC3_B7;

-- Node name is '~1068~1' 
-- Equation name is '~1068~1', location is LC8_B7, type is buried.
-- synthesized logic cell 
_LC8_B7  = LCELL( _EQ024);
  _EQ024 =  _LC5_B7 &  _LC8_B10
         # !_LC7_B6 &  _LC7_B7 & !_LC8_B10;

-- Node name is ':1082' 
-- Equation name is '_LC2_B7', type is buried 
_LC2_B7  = LCELL( _EQ025);
  _EQ025 =  flag1 &  _LC5_B7
         # !flag2 &  _LC5_B7;

-- Node name is '~1092~1' 
-- Equation name is '~1092~1', location is LC8_B10, type is buried.
-- synthesized logic cell 
!_LC8_B10 = _LC8_B10~NOT;
_LC8_B10~NOT = LCELL( _EQ026);
  _EQ026 = !_LC5_B6 & !_LC6_B6;

-- Node name is '~1092~2' 
-- Equation name is '~1092~2', location is LC1_B7, type is buried.
-- synthesized logic cell 
_LC1_B7  = LCELL( _EQ027);
  _EQ027 =  _LC5_B9 & !_LC8_B10
         #  _LC7_B6 & !_LC8_B10
         #  _LC4_B6;

-- Node name is '~1092~3' 
-- Equation name is '~1092~3', location is LC4_B7, type is buried.
-- synthesized logic cell 
_LC4_B7  = LCELL( _EQ028);
  _EQ028 =  _LC6_B12 &  _LC8_B10
         #  _LC2_B7 & !_LC7_B6 & !_LC8_B10;

-- Node name is '~1116~1' 
-- Equation name is '~1116~1', location is LC4_B1, type is buried.
-- synthesized logic cell 
_LC4_B1  = LCELL( _EQ029);
  _EQ029 = !_LC5_B6 &  _LC5_B9
         # !_LC5_B6 &  _LC7_B6;

-- Node name is '~1116~2' 
-- Equation name is '~1116~2', location is LC8_B12, type is buried.
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ030);
  _EQ030 = !_LC5_B6 &  _LC7_B12
         # !_LC5_B6 &  _LC6_B6
         #  _LC1_B6 &  _LC5_B6;

-- Node name is ':1133' 
-- Equation name is '_LC3_B6', type is buried 
_LC3_B6  = LCELL( _EQ031);
  _EQ031 = !flag0 & !flag1 &  flag2
         # !flag0 &  _LC1_B6
         #  flag1 &  flag2 &  _LC1_B6
         # !flag1 & !flag2 &  _LC1_B6;

-- Node name is '~1134~1' 
-- Equation name is '~1134~1', location is LC2_B4, type is buried.
-- synthesized logic cell 
_LC2_B4  = LCELL( _EQ032);
  _EQ032 =  _LC2_B12 &  _LC7_B6
         #  _LC6_B6;

-- Node name is ':1137' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = LCELL( _EQ033);
  _EQ033 =  _LC2_B12 &  _LC5_B6
         #  _LC3_B6 & !_LC5_B6
         #  _LC2_B4 & !_LC5_B6;

-- Node name is ':1152' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = LCELL( _EQ034);
  _EQ034 =  _LC2_B12 &  _LC3_B9
         #  _LC1_B6 &  _LC5_B9;

-- Node name is ':1155' 
-- Equation name is '_LC3_B12', type is buried 
_LC3_B12 = LCELL( _EQ035);
  _EQ035 =  _LC4_B5 &  _LC7_B6
         #  _LC1_B12 & !_LC7_B6;

-- Node name is ':1158' 
-- Equation name is '_LC4_B12', type is buried 
_LC4_B12 = LCELL( _EQ036);
  _EQ036 =  _LC3_B12 & !_LC6_B6
         #  _LC1_B6 &  _LC6_B6;

-- Node name is ':1161' 
-- Equation name is '_LC5_B12', type is buried 
_LC5_B12 = LCELL( _EQ037);
  _EQ037 =  _LC4_B12 & !_LC5_B6
         #  _LC4_B5 &  _LC5_B6;

-- Node name is ':1176' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = LCELL( _EQ038);
  _EQ038 =  _LC3_B9 &  _LC4_B5
         #  _LC2_B12 &  _LC5_B9;

-- Node name is ':1179' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ039);
  _EQ039 =  _LC1_B5 &  _LC7_B6
         #  _LC5_B5 & !_LC7_B6;

-- Node name is ':1182' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ040);
  _EQ040 =  _LC6_B5 & !_LC6_B6
         #  _LC2_B12 &  _LC6_B6;

-- Node name is ':1185' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ041);
  _EQ041 = !_LC5_B6 &  _LC7_B5
         #  _LC1_B5 &  _LC5_B6;

-- Node name is ':1200' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ042);
  _EQ042 =  _LC4_B5 &  _LC5_B9
         #  _LC1_B5 &  _LC3_B9;

-- Node name is ':1206' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ043);
  _EQ043 =  _LC4_B5 &  _LC6_B6
         #  _LC2_B5 & !_LC6_B6 & !_LC7_B6;

-- Node name is ':1252' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ044);
  _EQ044 =  _LC2_B12 &  _LC7_B6;

-- Node name is ':1254' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ045);
  _EQ045 =  _LC2_B4
         # !flag0 &  flag1 & !flag2
         #  flag0 &  flag2;

-- Node name is ':1277' 
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ046);
  _EQ046 = !flag0 & !flag1 &  flag2 &  _LC4_B5
         #  flag0 & !flag1 & !flag2
         #  flag0 &  flag1 &  flag2;

-- Node name is ':1278' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ047);
  _EQ047 =  _LC4_B5 &  _LC6_B6
         #  _LC1_B4 & !_LC6_B6
         #  _LC5_B4 & !_LC6_B6;

-- Node name is ':1281' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = LCELL( _EQ048);
  _EQ048 = !_LC5_B6 &  _LC6_B4
         #  _LC3_B7 &  _LC5_B6;

-- Node name is ':1382' 
-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ049);
  _EQ049 =  banner &  clk1
         # !banner &  clk2;



Project Information                                         g:\light\light.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,977K

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