📄 light.rpt
字号:
- 2 - B 06 DFFE 0 4 0 13 flag2 (:40)
- 3 - B 04 DFFE 0 5 0 14 flag1 (:41)
- 4 - B 04 DFFE 0 4 0 11 flag0 (:42)
- 7 - B 12 AND2 s 0 3 0 1 ~125~1
- 4 - B 06 AND2 0 3 0 11 :125
- 5 - B 06 AND2 0 3 0 10 :129
- 6 - B 06 OR2 ! 0 3 0 8 :133
- 7 - B 06 AND2 0 3 0 11 :137
- 5 - B 09 AND2 0 3 0 5 :141
- 1 - B 09 AND2 s ! 0 3 0 1 ~1020~1
- 6 - B 09 OR2 0 4 0 1 :1032
- 8 - B 09 OR2 0 4 0 1 :1038
- 3 - B 09 OR2 s 0 2 0 4 ~1058~1
- 7 - B 07 OR2 0 3 0 1 :1058
- 8 - B 07 OR2 s 0 4 0 1 ~1068~1
- 2 - B 07 OR2 0 3 0 1 :1082
- 8 - B 10 AND2 s ! 0 2 0 4 ~1092~1
- 1 - B 07 OR2 s 0 4 0 2 ~1092~2
- 4 - B 07 OR2 s 0 4 0 1 ~1092~3
- 4 - B 01 OR2 s 0 3 0 1 ~1116~1
- 8 - B 12 OR2 s 0 4 0 1 ~1116~2
- 3 - B 06 OR2 0 4 0 1 :1133
- 2 - B 04 OR2 s 0 3 0 2 ~1134~1
- 8 - B 06 OR2 0 4 0 1 :1137
- 1 - B 12 OR2 0 4 0 1 :1152
- 3 - B 12 OR2 0 3 0 1 :1155
- 4 - B 12 OR2 0 3 0 1 :1158
- 5 - B 12 OR2 0 3 0 1 :1161
- 5 - B 05 OR2 0 4 0 1 :1176
- 6 - B 05 OR2 0 3 0 1 :1179
- 7 - B 05 OR2 0 3 0 1 :1182
- 8 - B 05 OR2 0 3 0 1 :1185
- 2 - B 05 OR2 0 4 0 1 :1200
- 3 - B 05 OR2 0 4 0 1 :1206
- 1 - B 04 AND2 0 2 0 1 :1252
- 8 - B 04 OR2 0 4 0 1 :1254
- 5 - B 04 OR2 0 4 0 1 :1277
- 6 - B 04 OR2 0 4 0 1 :1278
- 7 - B 04 OR2 0 3 0 1 :1281
- 7 - B 09 OR2 1 2 0 12 :1382
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: g:\light\light.rpt
light
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 3/ 96( 3%) 20/ 48( 41%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\light\light.rpt
light
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 12 :1382
INPUT 2 clk1
Device-Specific Information: g:\light\light.rpt
light
** EQUATIONS **
clk1 : INPUT;
-- Node name is ':20' = 'banner'
-- Equation name is 'banner', location is LC2_B9, type is buried.
banner = DFFE( _EQ001, _LC7_B9, VCC, VCC, VCC);
_EQ001 = banner & _LC8_B10
# banner & _LC1_B9
# !banner & !_LC1_B9 & !_LC8_B10;
-- Node name is ':18' = 'clk2'
-- Equation name is 'clk2', location is LC4_B9, type is buried.
clk2 = DFFE(!clk2, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':42' = 'flag0'
-- Equation name is 'flag0', location is LC4_B4, type is buried.
flag0 = DFFE( _EQ002, _LC7_B9, VCC, VCC, VCC);
_EQ002 = !_LC4_B6 & _LC7_B4
# _LC4_B5 & _LC4_B6;
-- Node name is ':41' = 'flag1'
-- Equation name is 'flag1', location is LC3_B4, type is buried.
flag1 = DFFE( _EQ003, _LC7_B9, VCC, VCC, VCC);
_EQ003 = !_LC4_B6 & !_LC5_B6 & _LC8_B4
# !_LC3_B7 & !_LC4_B6 & _LC5_B6;
-- Node name is ':40' = 'flag2'
-- Equation name is 'flag2', location is LC2_B6, type is buried.
flag2 = DFFE( _EQ004, _LC7_B9, VCC, VCC, VCC);
_EQ004 = flag0 & flag1 & !_LC2_B12
# !flag1 & flag2
# flag0 & flag2;
-- Node name is 'light0'
-- Equation name is 'light0', type is output
light0 = _LC1_B5;
-- Node name is 'light1'
-- Equation name is 'light1', type is output
light1 = _LC4_B5;
-- Node name is 'light2'
-- Equation name is 'light2', type is output
light2 = _LC2_B12;
-- Node name is 'light3'
-- Equation name is 'light3', type is output
light3 = _LC1_B6;
-- Node name is 'light4'
-- Equation name is 'light4', type is output
light4 = _LC6_B12;
-- Node name is 'light5'
-- Equation name is 'light5', type is output
light5 = _LC5_B7;
-- Node name is 'light6'
-- Equation name is 'light6', type is output
light6 = _LC3_B7;
-- Node name is 'light7'
-- Equation name is 'light7', type is output
light7 = _LC6_B7;
-- Node name is ':2'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _EQ005, _LC7_B9, VCC, VCC, VCC);
_EQ005 = _LC3_B7 & _LC5_B6
# _LC4_B6
# !_LC5_B6 & _LC8_B9;
-- Node name is ':4'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = DFFE( _EQ006, _LC7_B9, VCC, VCC, VCC);
_EQ006 = _LC1_B7 & _LC6_B7
# !_LC4_B6 & _LC8_B7;
-- Node name is ':6'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = DFFE( _EQ007, _LC7_B9, VCC, VCC, VCC);
_EQ007 = _LC1_B7 & _LC3_B7
# !_LC4_B6 & _LC4_B7;
-- Node name is ':8'
-- Equation name is '_LC6_B12', type is buried
_LC6_B12 = DFFE( _EQ008, _LC7_B9, VCC, VCC, VCC);
_EQ008 = _LC4_B1 & _LC5_B7
# _LC4_B6 & _LC5_B7
# !_LC4_B6 & _LC8_B12;
-- Node name is ':10'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = DFFE( _EQ009, _LC7_B9, VCC, VCC, VCC);
_EQ009 = !_LC4_B6 & _LC8_B6
# _LC4_B6 & _LC6_B12;
-- Node name is ':12'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = DFFE( _EQ010, _LC7_B9, VCC, VCC, VCC);
_EQ010 = !_LC4_B6 & _LC5_B12
# _LC1_B6 & _LC4_B6;
-- Node name is ':14'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = DFFE( _EQ011, _LC7_B9, VCC, VCC, VCC);
_EQ011 = !_LC4_B6 & _LC8_B5
# _LC2_B12 & _LC4_B6;
-- Node name is ':16'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = DFFE( _EQ012, _LC7_B9, VCC, VCC, VCC);
_EQ012 = _LC4_B5 & _LC4_B6
# _LC3_B5 & !_LC4_B6 & !_LC5_B6;
-- Node name is '~125~1'
-- Equation name is '~125~1', location is LC7_B12, type is buried.
-- synthesized logic cell
_LC7_B12 = LCELL( _EQ013);
_EQ013 = _LC3_B9 & _LC6_B12 & !_LC7_B6;
-- Node name is ':125'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = LCELL( _EQ014);
_EQ014 = !flag0 & !flag1 & !flag2;
-- Node name is ':129'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ015);
_EQ015 = flag0 & !flag1 & !flag2;
-- Node name is ':133'
-- Equation name is '_LC6_B6', type is buried
!_LC6_B6 = _LC6_B6~NOT;
_LC6_B6~NOT = LCELL( _EQ016);
_EQ016 = flag2
# !flag1
# flag0;
-- Node name is ':137'
-- Equation name is '_LC7_B6', type is buried
_LC7_B6 = LCELL( _EQ017);
_EQ017 = flag0 & flag1 & !flag2;
-- Node name is ':141'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ018);
_EQ018 = !flag0 & !flag1 & flag2;
-- Node name is '~1020~1'
-- Equation name is '~1020~1', location is LC1_B9, type is buried.
-- synthesized logic cell
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ019);
_EQ019 = !flag0 & flag1 & flag2;
-- Node name is ':1032'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ020);
_EQ020 = !flag0 & !flag1 & flag2
# flag1 & _LC6_B7
# !flag0 & _LC6_B7
# !flag2 & _LC6_B7;
-- Node name is ':1038'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ021);
_EQ021 = !_LC6_B6 & _LC6_B9 & !_LC7_B6
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