fifo.tan.qmsg

来自「FIFO yibu de v daima」· QMSG 代码 · 共 22 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] fifo_wr clk_rd 8.290 ns register " "Info: tsu for register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]\" (data pin = \"fifo_wr\", clock pin = \"clk_rd\") is 8.290 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.215 ns + Longest pin register " "Info: + Longest pin to register delay is 11.215 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fifo_wr 1 PIN PIN_19 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_19; Fanout = 2; PIN Node = 'fifo_wr'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { fifo_wr } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.072 ns) + CELL(0.590 ns) 9.131 ns FIFO_ctl:FIFO_ctl_inst\|rd_en~13 2 COMB LC_X22_Y13_N8 3 " "Info: 2: + IC(7.072 ns) + CELL(0.590 ns) = 9.131 ns; Loc. = LC_X22_Y13_N8; Fanout = 3; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|rd_en~13'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.662 ns" { fifo_wr FIFO_ctl:FIFO_ctl_inst|rd_en~13 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.423 ns) 9.964 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[0\]~91 3 COMB LC_X22_Y13_N0 2 " "Info: 3: + IC(0.410 ns) + CELL(0.423 ns) = 9.964 ns; Loc. = LC_X22_Y13_N0; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[0\]~91'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.833 ns" { FIFO_ctl:FIFO_ctl_inst|rd_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.042 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[1\]~93 4 COMB LC_X22_Y13_N1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 10.042 ns; Loc. = LC_X22_Y13_N1; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[1\]~93'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.120 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[2\]~95 5 COMB LC_X22_Y13_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 10.120 ns; Loc. = LC_X22_Y13_N2; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[2\]~95'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.198 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]~87 6 COMB LC_X22_Y13_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 10.198 ns; Loc. = LC_X22_Y13_N3; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]~87'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 10.376 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[4\]~83 7 COMB LC_X22_Y13_N4 3 " "Info: 7: + IC(0.000 ns) + CELL(0.178 ns) = 10.376 ns; Loc. = LC_X22_Y13_N4; Fanout = 3; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[4\]~83'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 11.215 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 8 REG LC_X22_Y13_N5 10 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 11.215 ns; Loc. = LC_X22_Y13_N5; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.733 ns ( 33.29 % ) " "Info: Total cell delay = 3.733 ns ( 33.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.482 ns ( 66.71 % ) " "Info: Total interconnect delay = 7.482 ns ( 66.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.215 ns" { fifo_wr FIFO_ctl:FIFO_ctl_inst|rd_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.215 ns" { fifo_wr {} fifo_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|rd_en~13 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 7.072ns 0.410ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.590ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_rd destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_rd\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_rd 1 CLK PIN_29 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 23; CLK Node = 'clk_rd'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_rd } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 2 REG LC_X22_Y13_N5 10 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y13_N5; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.215 ns" { fifo_wr FIFO_ctl:FIFO_ctl_inst|rd_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.215 ns" { fifo_wr {} fifo_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|rd_en~13 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 7.072ns 0.410ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.590ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_rd empty FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 13.674 ns register " "Info: tco from clock \"clk_rd\" to destination pin \"empty\" through register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]\" is 13.674 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_rd source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk_rd\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_rd 1 CLK PIN_29 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 23; CLK Node = 'clk_rd'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_rd } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 2 REG LC_X22_Y13_N5 10 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y13_N5; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.488 ns + Longest register pin " "Info: + Longest register to pin delay is 10.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 1 REG LC_X22_Y13_N5 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y13_N5; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.590 ns) 1.770 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~324 2 COMB LC_X21_Y13_N3 1 " "Info: 2: + IC(1.180 ns) + CELL(0.590 ns) = 1.770 ns; Loc. = LC_X21_Y13_N3; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~324'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.770 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] FIFO_ctl:FIFO_ctl_inst|Equal1~324 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. =