prev_cmp_fifo.fit.qmsg

来自「FIFO yibu de v daima」· QMSG 代码 · 共 47 行 · 第 1/3 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.827 ns register register " "Info: Estimated most critical path is register to register delay of 6.827 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[1\] 1 REG LAB_X12_Y15 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y15; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[1\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(0.442 ns) 0.968 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~371 2 COMB LAB_X13_Y15 1 " "Info: 2: + IC(0.526 ns) + CELL(0.442 ns) = 0.968 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~371'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.968 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1] FIFO_ctl:FIFO_ctl_inst|Equal1~371 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 1.621 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~372 3 COMB LAB_X13_Y15 1 " "Info: 3: + IC(0.539 ns) + CELL(0.114 ns) = 1.621 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~372'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~371 FIFO_ctl:FIFO_ctl_inst|Equal1~372 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 2.274 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~373 4 COMB LAB_X13_Y15 1 " "Info: 4: + IC(0.539 ns) + CELL(0.114 ns) = 2.274 ns; Loc. = LAB_X13_Y15; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~373'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~372 FIFO_ctl:FIFO_ctl_inst|Equal1~373 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 2.927 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~374 5 COMB LAB_X13_Y15 2 " "Info: 5: + IC(0.539 ns) + CELL(0.114 ns) = 2.927 ns; Loc. = LAB_X13_Y15; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~374'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~373 FIFO_ctl:FIFO_ctl_inst|Equal1~374 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.590 ns) 3.819 ns FIFO_ctl:FIFO_ctl_inst\|full 6 COMB LAB_X12_Y15 82 " "Info: 6: + IC(0.302 ns) + CELL(0.590 ns) = 3.819 ns; Loc. = LAB_X12_Y15; Fanout = 82; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|full'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~374 FIFO_ctl:FIFO_ctl_inst|full } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 4.472 ns FIFO_ctl:FIFO_ctl_inst\|wr_en~13 7 COMB LAB_X12_Y15 3 " "Info: 7: + IC(0.063 ns) + CELL(0.590 ns) = 4.472 ns; Loc. = LAB_X12_Y15; Fanout = 3; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|wr_en~13'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { FIFO_ctl:FIFO_ctl_inst|full FIFO_ctl:FIFO_ctl_inst|wr_en~13 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.575 ns) 5.431 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[0\]~91COUT1 8 COMB LAB_X12_Y15 2 " "Info: 8: + IC(0.384 ns) + CELL(0.575 ns) = 5.431 ns; Loc. = LAB_X12_Y15; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[0\]~91COUT1'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.959 ns" { FIFO_ctl:FIFO_ctl_inst|wr_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0]~91COUT1 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.511 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[1\]~93COUT1 9 COMB LAB_X12_Y15 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 5.511 ns; Loc. = LAB_X12_Y15; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[1\]~93COUT1'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0]~91COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1]~93COUT1 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.591 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[2\]~97COUT1 10 COMB LAB_X12_Y15 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 5.591 ns; Loc. = LAB_X12_Y15; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[2\]~97COUT1'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1]~93COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2]~97COUT1 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.671 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]~85COUT1 11 COMB LAB_X12_Y15 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 5.671 ns; Loc. = LAB_X12_Y15; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]~85COUT1'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2]~97COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3]~85COUT1 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 5.929 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[4\]~83 12 COMB LAB_X12_Y15 3 " "Info: 12: + IC(0.000 ns) + CELL(0.258 ns) = 5.929 ns; Loc. = LAB_X12_Y15; Fanout = 3; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[4\]~83'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3]~85COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[4]~83 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 6.827 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[5\] 13 REG LAB_X12_Y15 12 " "Info: 13: + IC(0.000 ns) + CELL(0.898 ns) = 6.827 ns; Loc. = LAB_X12_Y15; Fanout = 12; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[4]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.935 ns ( 57.64 % ) " "Info: Total cell delay = 3.935 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.892 ns ( 42.36 % ) " "Info: Total interconnect delay = 2.892 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.827 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1] FIFO_ctl:FIFO_ctl_inst|Equal1~371 FIFO_ctl:FIFO_ctl_inst|Equal1~372 FIFO_ctl:FIFO_ctl_inst|Equal1~373 FIFO_ctl:FIFO_ctl_inst|Equal1~374 FIFO_ctl:FIFO_ctl_inst|full FIFO_ctl:FIFO_ctl_inst|wr_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0]~91COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1]~93COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2]~97COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3]~85COUT1 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[4]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X12_Y11 X23_Y21 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X12_Y11 to location X23_Y21" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FIFO_yibu/FIFO.fit.smsg " "Info: Generated suppressed messages file E:/FIFO_yibu/FIFO.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "184 " "Info: Peak virtual memory: 184 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 03 15:42:23 2008 " "Info: Processing ended: Thu Jul 03 15:42:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}