fifo.map.qmsg

来自「FIFO yibu de v daima」· QMSG 代码 · 共 31 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 03 15:44:20 2008 " "Info: Processing started: Thu Jul 03 15:44:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FIFO -c FIFO " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FIFO -c FIFO" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "full FULL FIFO_ctl.v(11) " "Info (10281): Verilog HDL Declaration information at FIFO_ctl.v(11): object \"full\" differs only in case from object \"FULL\" in the same scope" {  } { { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 11 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "empty EMPTY FIFO_ctl.v(9) " "Info (10281): Verilog HDL Declaration information at FIFO_ctl.v(9): object \"empty\" differs only in case from object \"EMPTY\" in the same scope" {  } { { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 9 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO_ctl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFO_ctl.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO_ctl " "Info: Found entity 1: FIFO_ctl" {  } { { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ram_128.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Ram_128.v" { { "Info" "ISGN_ENTITY_NAME" "1 Ram_128 " "Info: Found entity 1: Ram_128" {  } { { "Ram_128.v" "" { Text "E:/FIFO_yibu/Ram_128.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gray_gena.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gray_gena.v" { { "Info" "ISGN_ENTITY_NAME" "1 gray_gena " "Info: Found entity 1: gray_gena" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "G2B.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file G2B.v" { { "Info" "ISGN_ENTITY_NAME" "1 G2B " "Info: Found entity 1: G2B" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFO.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO " "Info: Found entity 1: FIFO" {  } { { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FIFO " "Info: Elaborating entity \"FIFO\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIFO_ctl FIFO_ctl:FIFO_ctl_inst " "Info: Elaborating entity \"FIFO_ctl\" for hierarchy \"FIFO_ctl:FIFO_ctl_inst\"" {  } { { "FIFO.v" "FIFO_ctl_inst" { Text "E:/FIFO_yibu/FIFO.v" 25 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gray_gena FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr " "Info: Elaborating entity \"gray_gena\" for hierarchy \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\"" {  } { { "FIFO_ctl.v" "gray_gena_inst_wr" { Text "E:/FIFO_yibu/FIFO_ctl.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "G2B FIFO_ctl:FIFO_ctl_inst\|G2B:G2B_wr " "Info: Elaborating entity \"G2B\" for hierarchy \"FIFO_ctl:FIFO_ctl_inst\|G2B:G2B_wr\"" {  } { { "FIFO_ctl.v" "G2B_wr" { Text "E:/FIFO_yibu/FIFO_ctl.v" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[6\] G2B.v(7) " "Warning (10755): Verilog HDL warning at G2B.v(7): assignments to Bin\[6\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 7 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[5\] G2B.v(8) " "Warning (10755): Verilog HDL warning at G2B.v(8): assignments to Bin\[5\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 8 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[4\] G2B.v(9) " "Warning (10755): Verilog HDL warning at G2B.v(9): assignments to Bin\[4\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 9 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[3\] G2B.v(10) " "Warning (10755): Verilog HDL warning at G2B.v(10): assignments to Bin\[3\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 10 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[2\] G2B.v(11) " "Warning (10755): Verilog HDL warning at G2B.v(11): assignments to Bin\[2\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 11 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[1\] G2B.v(12) " "Warning (10755): Verilog HDL warning at G2B.v(12): assignments to Bin\[1\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 12 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2076_UNCONVERTED" "Bin\[0\] G2B.v(13) " "Warning (10755): Verilog HDL warning at G2B.v(13): assignments to Bin\[0\] create a combinational loop" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 13 0 0 } }  } 0 10755 "Verilog HDL warning at %2!s!: assignments to %1!s! create a combinational loop" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Ram_128 Ram_128:Ram_128 " "Info: Elaborating entity \"Ram_128\" for hierarchy \"Ram_128:Ram_128\"" {  } { { "FIFO.v" "Ram_128" { Text "E:/FIFO_yibu/FIFO.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram Ram_128:Ram_128\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"Ram_128:Ram_128\|altsyncram:altsyncram_component\"" {  } { { "Ram_128.v" "altsyncram_component" { Text "E:/FIFO_yibu/Ram_128.v" 82 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Ram_128:Ram_128\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"Ram_128:Ram_128\|altsyncram:altsyncram_component\"" {  } { { "Ram_128.v" "" { Text "E:/FIFO_yibu/Ram_128.v" 82 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Ram_128:Ram_128\|altsyncram:altsyncram_component " "Info: Instantiated megafunction \"Ram_128:Ram_128\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Info: Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Info: Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Info: Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Info: Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Info: Parameter \"numwords_a\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Info: Parameter \"numwords_b\" = \"128\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Info: Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Info: Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK1 " "Info: Parameter \"outdata_reg_b\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Info: Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Info: Parameter \"widthad_a\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Info: Parameter \"widthad_b\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Info: Parameter \"width_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Info: Parameter \"width_b\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Info: Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "Ram_128.v" "" { Text "E:/FIFO_yibu/Ram_128.v" 82 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sig1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sig1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sig1 " "Info: Found entity 1: altsyncram_sig1" {  } { { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sig1 Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated " "Info: Elaborating entity \"altsyncram_sig1\" for hierarchy \"Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/80/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FIFO_yibu/FIFO.map.smsg " "Info: Generated suppressed messages file E:/FIFO_yibu/FIFO.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "80 " "Info: Implemented 80 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "49 " "Info: Implemented 49 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Peak virtual memory: 155 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 03 15:44:23 2008 " "Info: Processing ended: Thu Jul 03 15:44:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}