fifo.hif

FIFO yibu de v daima

Version 8.0 Build 215 05/29/2008 SJ Full Version
38
2468
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
soure|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
G2B
# storage
db|FIFO.(3).cnf
db|FIFO.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
G2B.v
f6cebf0a3199b994687b71d47f3bff3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr
FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd
}
# macro_sequence

# end
# entity
Ram_128
# storage
db|FIFO.(4).cnf
db|FIFO.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Ram_128.v
999a652d47d247ffa96f8d98f81206f
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Ram_128:Ram_128
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|FIFO.(5).cnf
db|FIFO.(5).cnf
# case_insensitive
# source_file
f:|altera|80|quartus|libraries|megafunctions|altsyncram.tdf
9a16746d1bf063b66fd125dd6a53b6d
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_sig1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_b
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
rden_a
-1
2
data_b
-1
2
clocken3
-1
2
clocken2
-1
2
clocken1
-1
2
clocken0
-1
2
byteena_b
-1
2
byteena_a
-1
2
}
# include_file {
f:|altera|80|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
f:|altera|80|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
f:|altera|80|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
f:|altera|80|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
f:|altera|80|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
f:|altera|80|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
f:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
f:|altera|80|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
f:|altera|80|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
}
# hierarchies {
Ram_128:Ram_128|altsyncram:altsyncram_component
}
# macro_sequence

# end
# entity
altsyncram_sig1
# storage
db|FIFO.(6).cnf
db|FIFO.(6).cnf
# case_insensitive
# source_file
db|altsyncram_sig1.tdf
673b64f83522d67566f1e153caf4ba5a
6
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated
}
# macro_sequence

# end
# entity
gray_gena
# storage
db|FIFO.(2).cnf
db|FIFO.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
gray_gena.v
c1e0efa612e25defd5dff5b4caf8252e
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr
FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd
}
# macro_sequence

# end
# entity
FIFO
# storage
db|FIFO.(0).cnf
db|FIFO.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
FIFO.v
bbbe525fa3d22c86abbfde99d20c7c8
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
FIFO_ctl
# storage
db|FIFO.(1).cnf
db|FIFO.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
FIFO_ctl.v
b89c17ca3b447275e6890644b7af
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FULL
1
PARAMETER_UNSIGNED_BIN
DEF
EMPTY
1
PARAMETER_UNSIGNED_BIN
DEF
ACTIVE
0
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
FIFO_ctl:FIFO_ctl_inst
}
# macro_sequence

# end
# complete