fifo.hier_info

FIFO yibu de v daima

|FIFO
clk_wr => clk_wr~0.IN2
clk_rd => clk_rd~0.IN2
rst => rst~0.IN1
fifo_wr => fifo_wr~0.IN1
fifo_rd => fifo_rd~0.IN1
data_in[0] => data_in[0]~7.IN1
data_in[1] => data_in[1]~6.IN1
data_in[2] => data_in[2]~5.IN1
data_in[3] => data_in[3]~4.IN1
data_in[4] => data_in[4]~3.IN1
data_in[5] => data_in[5]~2.IN1
data_in[6] => data_in[6]~1.IN1
data_in[7] => data_in[7]~0.IN1
empty <= FIFO_ctl:FIFO_ctl_inst.empty
full <= FIFO_ctl:FIFO_ctl_inst.full
data_out[0] <= Ram_128:Ram_128.q
data_out[1] <= Ram_128:Ram_128.q
data_out[2] <= Ram_128:Ram_128.q
data_out[3] <= Ram_128:Ram_128.q
data_out[4] <= Ram_128:Ram_128.q
data_out[5] <= Ram_128:Ram_128.q
data_out[6] <= Ram_128:Ram_128.q
data_out[7] <= Ram_128:Ram_128.q


|FIFO|FIFO_ctl:FIFO_ctl_inst
clk_wr => clk_wr~0.IN1
clk_rd => clk_rd~0.IN1
rst => rst~0.IN2
fifo_wr => rd_en~0.IN0
fifo_wr => wr_en~1.OUTPUTSELECT
fifo_wr => wr_en~0.IN0
fifo_rd => rd_en~1.OUTPUTSELECT
fifo_rd => rd_en~0.IN1
fifo_rd => wr_en~0.IN1
wr_ptr[0] <= G2B:G2B_wr.Bin
wr_ptr[1] <= G2B:G2B_wr.Bin
wr_ptr[2] <= G2B:G2B_wr.Bin
wr_ptr[3] <= G2B:G2B_wr.Bin
wr_ptr[4] <= G2B:G2B_wr.Bin
wr_ptr[5] <= G2B:G2B_wr.Bin
wr_ptr[6] <= G2B:G2B_wr.Bin
wr_ptr[7] <= G2B:G2B_wr.Bin
rd_ptr[0] <= G2B:G2B_rd.Bin
rd_ptr[1] <= G2B:G2B_rd.Bin
rd_ptr[2] <= G2B:G2B_rd.Bin
rd_ptr[3] <= G2B:G2B_rd.Bin
rd_ptr[4] <= G2B:G2B_rd.Bin
rd_ptr[5] <= G2B:G2B_rd.Bin
rd_ptr[6] <= G2B:G2B_rd.Bin
rd_ptr[7] <= G2B:G2B_rd.Bin
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
full <= full~1.DB_MAX_OUTPUT_PORT_TYPE


|FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr
clk => bin[7].CLK
clk => bin[6].CLK
clk => bin[5].CLK
clk => bin[4].CLK
clk => bin[3].CLK
clk => bin[2].CLK
clk => bin[1].CLK
clk => bin[0].CLK
clr => always0~0.IN0
en => bin~7.OUTPUTSELECT
en => bin~6.OUTPUTSELECT
en => bin~5.OUTPUTSELECT
en => bin~4.OUTPUTSELECT
en => bin~3.OUTPUTSELECT
en => bin~2.OUTPUTSELECT
en => bin~1.OUTPUTSELECT
en => bin~0.OUTPUTSELECT
gray_count[0] <= gray_count~6.DB_MAX_OUTPUT_PORT_TYPE
gray_count[1] <= gray_count~5.DB_MAX_OUTPUT_PORT_TYPE
gray_count[2] <= gray_count~4.DB_MAX_OUTPUT_PORT_TYPE
gray_count[3] <= gray_count~3.DB_MAX_OUTPUT_PORT_TYPE
gray_count[4] <= gray_count~2.DB_MAX_OUTPUT_PORT_TYPE
gray_count[5] <= gray_count~1.DB_MAX_OUTPUT_PORT_TYPE
gray_count[6] <= gray_count~0.DB_MAX_OUTPUT_PORT_TYPE
gray_count[7] <= bin[7].DB_MAX_OUTPUT_PORT_TYPE


|FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd
clk => bin[7].CLK
clk => bin[6].CLK
clk => bin[5].CLK
clk => bin[4].CLK
clk => bin[3].CLK
clk => bin[2].CLK
clk => bin[1].CLK
clk => bin[0].CLK
clr => always0~0.IN0
en => bin~7.OUTPUTSELECT
en => bin~6.OUTPUTSELECT
en => bin~5.OUTPUTSELECT
en => bin~4.OUTPUTSELECT
en => bin~3.OUTPUTSELECT
en => bin~2.OUTPUTSELECT
en => bin~1.OUTPUTSELECT
en => bin~0.OUTPUTSELECT
gray_count[0] <= gray_count~6.DB_MAX_OUTPUT_PORT_TYPE
gray_count[1] <= gray_count~5.DB_MAX_OUTPUT_PORT_TYPE
gray_count[2] <= gray_count~4.DB_MAX_OUTPUT_PORT_TYPE
gray_count[3] <= gray_count~3.DB_MAX_OUTPUT_PORT_TYPE
gray_count[4] <= gray_count~2.DB_MAX_OUTPUT_PORT_TYPE
gray_count[5] <= gray_count~1.DB_MAX_OUTPUT_PORT_TYPE
gray_count[6] <= gray_count~0.DB_MAX_OUTPUT_PORT_TYPE
gray_count[7] <= bin[7].DB_MAX_OUTPUT_PORT_TYPE


|FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr
gray[0] => ~NO_FANOUT~
gray[1] => Bin~6.IN1
gray[2] => Bin~5.IN1
gray[3] => Bin~4.IN1
gray[4] => Bin~3.IN1
gray[5] => Bin~2.IN1
gray[6] => Bin~1.IN1
gray[7] => Bin~0.IN1
gray[7] => Bin[7].DATAIN
Bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE


|FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd
gray[0] => ~NO_FANOUT~
gray[1] => Bin~6.IN1
gray[2] => Bin~5.IN1
gray[3] => Bin~4.IN1
gray[4] => Bin~3.IN1
gray[5] => Bin~2.IN1
gray[6] => Bin~1.IN1
gray[7] => Bin~0.IN1
gray[7] => Bin[7].DATAIN
Bin[7] <= gray[7].DB_MAX_OUTPUT_PORT_TYPE


|FIFO|Ram_128:Ram_128
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdaddress[0] => rdaddress[0]~6.IN1
rdaddress[1] => rdaddress[1]~5.IN1
rdaddress[2] => rdaddress[2]~4.IN1
rdaddress[3] => rdaddress[3]~3.IN1
rdaddress[4] => rdaddress[4]~2.IN1
rdaddress[5] => rdaddress[5]~1.IN1
rdaddress[6] => rdaddress[6]~0.IN1
rdclock => rdclock~0.IN1
wraddress[0] => wraddress[0]~6.IN1
wraddress[1] => wraddress[1]~5.IN1
wraddress[2] => wraddress[2]~4.IN1
wraddress[3] => wraddress[3]~3.IN1
wraddress[4] => wraddress[4]~2.IN1
wraddress[5] => wraddress[5]~1.IN1
wraddress[6] => wraddress[6]~0.IN1
wrclock => wrclock~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b


|FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component
wren_a => altsyncram_sig1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_sig1:auto_generated.data_a[0]
data_a[1] => altsyncram_sig1:auto_generated.data_a[1]
data_a[2] => altsyncram_sig1:auto_generated.data_a[2]
data_a[3] => altsyncram_sig1:auto_generated.data_a[3]
data_a[4] => altsyncram_sig1:auto_generated.data_a[4]
data_a[5] => altsyncram_sig1:auto_generated.data_a[5]
data_a[6] => altsyncram_sig1:auto_generated.data_a[6]
data_a[7] => altsyncram_sig1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_sig1:auto_generated.address_a[0]
address_a[1] => altsyncram_sig1:auto_generated.address_a[1]
address_a[2] => altsyncram_sig1:auto_generated.address_a[2]
address_a[3] => altsyncram_sig1:auto_generated.address_a[3]
address_a[4] => altsyncram_sig1:auto_generated.address_a[4]
address_a[5] => altsyncram_sig1:auto_generated.address_a[5]
address_a[6] => altsyncram_sig1:auto_generated.address_a[6]
address_b[0] => altsyncram_sig1:auto_generated.address_b[0]
address_b[1] => altsyncram_sig1:auto_generated.address_b[1]
address_b[2] => altsyncram_sig1:auto_generated.address_b[2]
address_b[3] => altsyncram_sig1:auto_generated.address_b[3]
address_b[4] => altsyncram_sig1:auto_generated.address_b[4]
address_b[5] => altsyncram_sig1:auto_generated.address_b[5]
address_b[6] => altsyncram_sig1:auto_generated.address_b[6]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_sig1:auto_generated.clock0
clock1 => altsyncram_sig1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_sig1:auto_generated.q_b[0]
q_b[1] <= altsyncram_sig1:auto_generated.q_b[1]
q_b[2] <= altsyncram_sig1:auto_generated.q_b[2]
q_b[3] <= altsyncram_sig1:auto_generated.q_b[3]
q_b[4] <= altsyncram_sig1:auto_generated.q_b[4]
q_b[5] <= altsyncram_sig1:auto_generated.q_b[5]
q_b[6] <= altsyncram_sig1:auto_generated.q_b[6]
q_b[7] <= altsyncram_sig1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0