fifo.v

FIFO yibu de v daima

module FIFO(input clk_wr,
			input clk_rd,
			input rst,
			input fifo_wr,
			input fifo_rd,
			input [7:0] data_in,

			output  empty,
			output  full,
			output [7:0] data_out
			);
wire [7:0] wr_addr;
wire [7:0] rd_addr;
			
FIFO_ctl  FIFO_ctl_inst (.clk_wr(clk_wr),
						 .clk_rd(clk_rd),
						 .rst(rst),
						 .fifo_wr(fifo_wr),
						 .fifo_rd(fifo_rd),

						 .wr_ptr(wr_addr),
						 .rd_ptr(rd_addr),
						 .empty(empty),
						 .full(full)
						);

Ram_128 Ram_128(.data(data_in),
				.rdaddress(rd_addr[6:0]),
				.rdclock(clk_rd),
				.wraddress(wr_addr[6:0]),
				.wrclock(clk_wr),
				.wren(!full),
				.q(data_out)
				);
				
endmodule