📄 fifo.sim.rpt
字号:
; |FIFO|data_in[4] ; |FIFO|data_in[4]~corein ; combout ;
; |FIFO|data_in[5] ; |FIFO|data_in[5]~corein ; combout ;
; |FIFO|data_in[6] ; |FIFO|data_in[6]~corein ; combout ;
; |FIFO|data_in[7] ; |FIFO|data_in[7]~corein ; combout ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 ; cout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5]~85 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5]~85COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5]~85 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6]~89 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6]~89COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6]~89 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95COUT1 ; cout1 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[0] ; portbdataout0 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[1] ; portbdataout1 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[2] ; portbdataout2 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[3] ; portbdataout3 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[4] ; portbdataout4 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[5] ; portbdataout5 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[6] ; portbdataout6 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[7] ; portbdataout7 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~61 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~61 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~62 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~62 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~61 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~61 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~63 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~63 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|rd_en~13 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|rd_en~13 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~6 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~6 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~5 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~5 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~4 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~4 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~3 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~3 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~2 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~2 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~1 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~1 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~0 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~0 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~6 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~6 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~5 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~5 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~4 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~4 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~3 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~3 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~2 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~2 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~1 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~1 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~0 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~0 ; combout ;
; |FIFO|data_out[0] ; |FIFO|data_out[0] ; padio ;
; |FIFO|data_out[1] ; |FIFO|data_out[1] ; padio ;
; |FIFO|data_out[2] ; |FIFO|data_out[2] ; padio ;
; |FIFO|data_out[3] ; |FIFO|data_out[3] ; padio ;
; |FIFO|data_out[4] ; |FIFO|data_out[4] ; padio ;
; |FIFO|data_out[5] ; |FIFO|data_out[5] ; padio ;
; |FIFO|data_out[6] ; |FIFO|data_out[6] ; padio ;
; |FIFO|data_out[7] ; |FIFO|data_out[7] ; padio ;
; |FIFO|rst ; |FIFO|rst~corein ; combout ;
; |FIFO|fifo_rd ; |FIFO|fifo_rd~corein ; combout ;
; |FIFO|data_in[0] ; |FIFO|data_in[0]~corein ; combout ;
; |FIFO|data_in[1] ; |FIFO|data_in[1]~corein ; combout ;
; |FIFO|data_in[2] ; |FIFO|data_in[2]~corein ; combout ;
; |FIFO|data_in[3] ; |FIFO|data_in[3]~corein ; combout ;
; |FIFO|data_in[4] ; |FIFO|data_in[4]~corein ; combout ;
; |FIFO|data_in[5] ; |FIFO|data_in[5]~corein ; combout ;
; |FIFO|data_in[6] ; |FIFO|data_in[6]~corein ; combout ;
; |FIFO|data_in[7] ; |FIFO|data_in[7]~corein ; combout ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Thu Jul 03 17:17:57 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off FIFO -c FIFO
Info: Using vector source file "E:/FIFO_yibu/FIFO.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 30.00 %
Info: Number of transitions in simulation is 2536
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 110 megabytes
Info: Processing ended: Thu Jul 03 17:17:58 2008
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -