📄 fifo.sim.rpt
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; Total nodes checked ; 73 ;
; Total output ports checked ; 90 ;
; Total output ports with complete 1/0-value coverage ; 27 ;
; Total output ports with no 1/0-value coverage ; 58 ;
; Total output ports with no 1-value coverage ; 60 ;
; Total output ports with no 0-value coverage ; 61 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+---------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[4] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[4]~83 ; cout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5]~85COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3]~87 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3]~87COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6]~89COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0]~91 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[0]~91COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1]~93 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[1]~93COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2]~95 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[2]~95COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~324 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~324 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~325 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~325 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~326 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~326 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~327 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~327 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~328 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~328 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~329 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~329 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~330 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~330 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~331 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~331 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~332 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~332 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|full ; |FIFO|FIFO_ctl:FIFO_ctl_inst|full ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~62 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~62 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|wr_en~13 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|wr_en~13 ; combout ;
; |FIFO|full ; |FIFO|full ; padio ;
; |FIFO|clk_rd ; |FIFO|clk_rd~corein ; combout ;
; |FIFO|clk_wr ; |FIFO|clk_wr~corein ; combout ;
; |FIFO|fifo_wr ; |FIFO|fifo_wr~corein ; combout ;
+---------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~83 ; cout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5]~85 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5]~85COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[5]~85 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~87COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6]~89 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[6]~89COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6]~89 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93COUT1 ; cout1 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95 ; cout0 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2] ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~95COUT1 ; cout1 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[0] ; portbdataout0 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[1] ; portbdataout1 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[2] ; portbdataout2 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[3] ; portbdataout3 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[4] ; portbdataout4 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[5] ; portbdataout5 ;
; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0 ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|q_b[7] ; portbdataout7 ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~333 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|Equal1~333 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~61 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~61 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~62 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~62 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~61 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~61 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~63 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|always0~63 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|rd_en~13 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|rd_en~13 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~6 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~6 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~5 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~5 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~4 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~4 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~3 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~3 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~2 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~2 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~1 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~1 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~0 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin~0 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~6 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~6 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~5 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~5 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~4 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~4 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~3 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~3 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~2 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~2 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~1 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~1 ; combout ;
; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~0 ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin~0 ; combout ;
; |FIFO|empty ; |FIFO|empty ; padio ;
; |FIFO|data_out[0] ; |FIFO|data_out[0] ; padio ;
; |FIFO|data_out[1] ; |FIFO|data_out[1] ; padio ;
; |FIFO|data_out[2] ; |FIFO|data_out[2] ; padio ;
; |FIFO|data_out[3] ; |FIFO|data_out[3] ; padio ;
; |FIFO|data_out[4] ; |FIFO|data_out[4] ; padio ;
; |FIFO|data_out[5] ; |FIFO|data_out[5] ; padio ;
; |FIFO|data_out[7] ; |FIFO|data_out[7] ; padio ;
; |FIFO|fifo_rd ; |FIFO|fifo_rd~corein ; combout ;
; |FIFO|data_in[0] ; |FIFO|data_in[0]~corein ; combout ;
; |FIFO|data_in[1] ; |FIFO|data_in[1]~corein ; combout ;
; |FIFO|data_in[2] ; |FIFO|data_in[2]~corein ; combout ;
; |FIFO|data_in[3] ; |FIFO|data_in[3]~corein ; combout ;
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