gray_gena.v

FIFO yibu de v daima

module gray_gena(input clk,
				 input clr,
				 input en,
				 output reg [7:0] gray_count
				 );
reg  [7:0] bin;

always@(posedge clk)
	begin
		if( !clr && bin == 8'b1111_1111)
			bin <= 0;
		else
			begin
				if ( !en )
					bin <= bin + 1'b1;
				else
					bin <=bin;
			end
	end

always@(bin)
	begin
		gray_count[7] <= bin[7];
		gray_count[6] <= bin[7] ^ bin[6] ;
		gray_count[5] <= bin[6] ^ bin[5] ;
		gray_count[4] <= bin[5] ^ bin[4] ;
		gray_count[3] <= bin[4] ^ bin[3] ;
		gray_count[2] <= bin[3] ^ bin[2] ;
		gray_count[1] <= bin[2] ^ bin[1] ;
		gray_count[0] <= bin[1] ^ bin[0] ;
	end

endmodule