fifo.map.rpt

FIFO yibu de v daima

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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Ram_128:Ram_128|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+----------------------------------+
; Parameter Name                     ; Value                ; Type                             ;
+------------------------------------+----------------------+----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                          ;
; WIDTH_A                            ; 8                    ; Signed Integer                   ;
; WIDTHAD_A                          ; 7                    ; Signed Integer                   ;
; NUMWORDS_A                         ; 128                  ; Signed Integer                   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                          ;
; WIDTH_B                            ; 8                    ; Signed Integer                   ;
; WIDTHAD_B                          ; 7                    ; Signed Integer                   ;
; NUMWORDS_B                         ; 128                  ; Signed Integer                   ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                          ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                          ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                          ;
; OUTDATA_REG_B                      ; CLOCK1               ; Untyped                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                   ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                          ;
; BYTE_SIZE                          ; 8                    ; Untyped                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
; INIT_FILE                          ; UNUSED               ; Untyped                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                          ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                          ;
; DEVICE_FAMILY                      ; Cyclone              ; Untyped                          ;
; CBXI_PARAMETER                     ; altsyncram_sig1      ; Untyped                          ;
+------------------------------------+----------------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Thu Jul 03 15:44:20 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FIFO -c FIFO
Info: Found 1 design units, including 1 entities, in source file FIFO_ctl.v
    Info: Found entity 1: FIFO_ctl
Info: Found 1 design units, including 1 entities, in source file Ram_128.v
    Info: Found entity 1: Ram_128
Info: Found 1 design units, including 1 entities, in source file gray_gena.v
    Info: Found entity 1: gray_gena
Info: Found 1 design units, including 1 entities, in source file G2B.v
    Info: Found entity 1: G2B
Info: Found 1 design units, including 1 entities, in source file FIFO.v
    Info: Found entity 1: FIFO
Info: Elaborating entity "FIFO" for the top level hierarchy
Info: Elaborating entity "FIFO_ctl" for hierarchy "FIFO_ctl:FIFO_ctl_inst"
Info: Elaborating entity "gray_gena" for hierarchy "FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr"
Info: Elaborating entity "G2B" for hierarchy "FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr"
Warning (10755): Verilog HDL warning at G2B.v(7): assignments to Bin[6] create a combinational loop
Warning (10755): Verilog HDL warning at G2B.v(8): assignments to Bin[5] create a combinational loop
Warning (10755): Verilog HDL warning at G2B.v(9): assignments to Bin[4] create a combinational loop
Warning (10755): Verilog HDL warning at G2B.v(10): assignments to Bin[3] create a combinational loop
Warning (10755): Verilog HDL warning at G2B.v(11): assignments to Bin[2] create a combinational loop
Warning (10755): Verilog HDL warning at G2B.v(12): assignments to Bin[1] create a combinational loop
Warning (10755): Verilog HDL warning at G2B.v(13): assignments to Bin[0] create a combinational loop
Info: Elaborating entity "Ram_128" for hierarchy "Ram_128:Ram_128"
Info: Elaborating entity "altsyncram" for hierarchy "Ram_128:Ram_128|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "Ram_128:Ram_128|altsyncram:altsyncram_component"
Info: Instantiated megafunction "Ram_128:Ram_128|altsyncram:altsyncram_component" with the following parameter:
    Info: Parameter "address_aclr_a" = "NONE"
    Info: Parameter "address_aclr_b" = "NONE"
    Info: Parameter "address_reg_b" = "CLOCK1"
    Info: Parameter "indata_aclr_a" = "NONE"
    Info: Parameter "intended_device_family" = "Cyclone"
    Info: Parameter "lpm_type" = "altsyncram"
    Info: Parameter "numwords_a" = "128"
    Info: Parameter "numwords_b" = "128"
    Info: Parameter "operation_mode" = "DUAL_PORT"
    Info: Parameter "outdata_aclr_b" = "NONE"
    Info: Parameter "outdata_reg_b" = "CLOCK1"
    Info: Parameter "power_up_uninitialized" = "FALSE"
    Info: Parameter "widthad_a" = "7"
    Info: Parameter "widthad_b" = "7"
    Info: Parameter "width_a" = "8"
    Info: Parameter "width_b" = "8"
    Info: Parameter "width_byteena_a" = "1"
    Info: Parameter "wrcontrol_aclr_a" = "NONE"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sig1.tdf
    Info: Found entity 1: altsyncram_sig1
Info: Elaborating entity "altsyncram_sig1" for hierarchy "Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated"
Info: Generated suppressed messages file E:/FIFO_yibu/FIFO.map.smsg
Info: Implemented 80 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 10 output pins
    Info: Implemented 49 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 155 megabytes
    Info: Processing ended: Thu Jul 03 15:44:23 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/FIFO_yibu/FIFO.map.smsg.