📄 fifo.map.rpt
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+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; FIFO_ctl.v ; yes ; User Verilog HDL File ; E:/FIFO_yibu/FIFO_ctl.v ;
; Ram_128.v ; yes ; User Verilog HDL File ; E:/FIFO_yibu/Ram_128.v ;
; gray_gena.v ; yes ; User Verilog HDL File ; E:/FIFO_yibu/gray_gena.v ;
; G2B.v ; yes ; User Verilog HDL File ; E:/FIFO_yibu/G2B.v ;
; FIFO.v ; yes ; User Verilog HDL File ; E:/FIFO_yibu/FIFO.v ;
; altsyncram.tdf ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/lpm_decode.inc ;
; aglobal80.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; f:/altera/80/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_sig1.tdf ; yes ; Auto-Generated Megafunction ; E:/FIFO_yibu/db/altsyncram_sig1.tdf ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------+
; Resource ; Usage ;
+---------------------------------------------+--------+
; Total logic elements ; 49 ;
; -- Combinational with no register ; 33 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 16 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 13 ;
; -- 3 input functions ; 18 ;
; -- 2 input functions ; 18 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 35 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 16 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 16 ;
; Total logic cells in carry chains ; 16 ;
; I/O pins ; 23 ;
; Total memory bits ; 1024 ;
; Maximum fan-out node ; clk_rd ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 328 ;
; Average fan-out ; 4.10 ;
+---------------------------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------+--------------+
; |FIFO ; 49 (0) ; 16 ; 1024 ; 23 ; 0 ; 33 (0) ; 0 (0) ; 16 (0) ; 16 (0) ; 0 (0) ; |FIFO ; work ;
; |FIFO_ctl:FIFO_ctl_inst| ; 49 (13) ; 16 ; 0 ; 0 ; 0 ; 33 (13) ; 0 (0) ; 16 (0) ; 16 (0) ; 0 (0) ; |FIFO|FIFO_ctl:FIFO_ctl_inst ; work ;
; |G2B:G2B_rd| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd ; work ;
; |G2B:G2B_wr| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FIFO|FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr ; work ;
; |gray_gena:gray_gena_inst_rd| ; 11 (11) ; 8 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd ; work ;
; |gray_gena:gray_gena_inst_wr| ; 11 (11) ; 8 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |FIFO|FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr ; work ;
; |Ram_128:Ram_128| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FIFO|Ram_128:Ram_128 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component ; work ;
; |altsyncram_sig1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |FIFO|Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated ; work ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 8 ; 128 ; 8 ; 1024 ; None ;
+-------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+-------------------------------------------------------------+
; Logic Cells Representing Combinational Loops ;
+--------------------------------------------------------+----+
; Logic Cell Name ; ;
+--------------------------------------------------------+----+
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[0] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[1] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[2] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[3] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[4] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[5] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_wr|Bin[6] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[0] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[1] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[2] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[3] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[4] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[5] ; ;
; FIFO_ctl:FIFO_ctl_inst|G2B:G2B_rd|Bin[6] ; ;
; Number of logic cells representing combinational loops ; 14 ;
+--------------------------------------------------------+----+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 16 ;
; Number of registers using Synchronous Clear ; 16 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------+
; Source assignments for Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------+
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FIFO_ctl:FIFO_ctl_inst ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------+
; FULL ; 1 ; Unsigned Binary ;
; EMPTY ; 1 ; Unsigned Binary ;
; ACTIVE ; 0 ; Unsigned Binary ;
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