fifo_ctl.v.bak

FIFO yibu de v daima

module FIFO_ctl(input clk_wr,
				input clk_rd,
				input rst,
				input fifo_wr,
				input fifo_rd,
			
				output [7:0] wr_ptr,
				output [7:0] rd_ptr,
				output  empty,
				output  full,
				output reg[7:0] ss
				);
				
parameter FULL = 1'b1,
		  EMPTY = 1'b1,
		  ACTIVE = 1'b0;
		  
wire [7:0] gcount_wr;
wire [7:0] gcount_rd;
wire wr_en;
wire rd_en;


assign full = ( (gcount_wr[6:0] == gcount_rd[6:0]) && (gcount_wr[7] != gcount_rd[7]) ) 
				? FULL : ACTIVE;
assign empty = ( gcount_wr == gcount_rd ) ? EMPTY : ACTIVE;

assign wr_en = ( fifo_wr && fifo_rd )? 1'b1 : ( fifo_wr? (full?  1'b1 : 1'b0)  : 1'b1 );
assign rd_en = ( fifo_wr && fifo_rd )? 1'b1 : ( fifo_rd? (empty? 1'b1 : 1'b0)  : 1'b1 );

gray_gena  gray_gena_inst_wr (.clk(clk_wr),
							  .clr(rst),
							  .en(wr_en),
							  .gray_count(gcount_wr)
							  );
always@(posedge clk_wr)
	ss <= gcount_wr;
							  
gray_gena  gray_gena_inst_rd (.clk(clk_rd),
							  .clr(rst),
							  .en(rd_en),
							  .gray_count(gcount_rd)
							  );

G2B  G2B_wr (.gray(gcount_wr),
			 .Bin(wr_ptr));
			 
G2B  G2B_rd (.gray(gcount_rd),
			 .Bin(rd_ptr));

endmodule