rominit.s

rom.init for powerpc bootloader

/* romInit.s - Freescale mds837x ROM initialization module */

/*
 * Copyright (c) 2005, 2007 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01b,20oct07,x_s  modified for mds837x.
01a,19jan05,dtr  written from ads834x/romInit.s/01f
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 8 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include <vxWorks.h>
#include <asm.h>
#include <cacheLib.h>
#include "config.h"
#include <regs.h>	
#include <sysLib.h>

 

#define WRITEADR(reg1,reg2,addr32,val) \
	lis	reg1, HI(addr32); \
	ori	reg1, reg1, LO(addr32); \
	lis	reg2, HI(val); \
	ori	reg2, reg2, LO(val); \
	stw	reg2, 0(reg1)

#define WRITEOFFSET(regbase,reg2,offset,val) \
        lis	reg2, HI(val); \
        ori	reg2, reg2, LO(val); \
	stw	reg2, offset(regbase);
	
	/* internals */

	FUNC_EXPORT(_romInit)		/* start of system code */
	FUNC_EXPORT(romInit)		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
/* 
Hard Reset Configuration Word (HRCW) See config.h/bnc837x.h/target.ref for 
more info
*/
 .fill   8,1,HRCW_LOW_BYTE0 
 .fill   8,1,HRCW_LOW_BYTE1 
 .fill   8,1,HRCW_LOW_BYTE2 
 .fill   8,1,HRCW_LOW_BYTE3
 .fill   8,1,HRCW_HIGH_BYTE0 
 .fill   8,1,HRCW_HIGH_BYTE1 
 .fill   8,1,HRCW_HIGH_BYTE2 
 .fill   8,1,HRCW_HIGH_BYTE3

 .fill   192,1,0     /* The rest of the space are filled with zeros */

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:

    bl	cold		/* jump to the cold boot initialization */
	nop
	bl	warm		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-2007 Wind River Systems, Inc."
	.align 2

cold:
        li      r11, BOOT_COLD   /* set cold boot as start type */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification. The default IMMR base address was 0xFF400000,
	 * as originally programmed in the Hard Reset Configuration Word.
	 */


	lis	r4, HI (CCSBAR)	
	ori	r4, r4, LO (CCSBAR)
#ifndef BOOT_FROM_UBOOT	
	lis     r8,HIADJ(CCSBAR_INIT)	/* IMMR was at 0xff400000 */
	ori     r8, r8, LO(CCSBAR_INIT)	/* IMMR now at CCSBAR */
	stw     r4,0(r8)
	isync
	sync
#endif 
	         
    lis     r5, 0x0040
    stw     r5, M83XX_SPCR(0)(r4)

	
	/* 
	Modifying ACR to increase pipeline depth, must retain 
	rsvd bits values.
	*/	
    lis     r6, 0x0010
	ori     r6, r6, 0x0000
    stw     r6, M83XX_ACR(0)(r4)

    sync
    isync
			
    
#ifndef BOOT_FROM_UBOOT			
	lis  r5, HIADJ(QUICC_OR0(CCSBAR))
	addi r5, r5, LO(QUICC_OR0(CCSBAR))

	lwz  r6, 0(r5)
	ori  r6, r6, 0x0ff7
	stw  r6, 0(r5) 
	isync			/* synchronize */


#ifdef BMS_HIGH_ENABLE
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,1), FLASH_BASE_ADRS)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,1), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_64MB ) )

	
	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,1))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,1))
	lwz  r7,0(r6)
	
	isync
	
#else
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,0), 0x00000000)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,0), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_2GB ))

	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,0))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,0))
	lwz  r7,0(r6)
	
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,1), 0x80000000)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,1), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_2GB ) )
	
	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,1))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,1))
	lwz  r7,0(r6)
	
	isync
#endif		
#endif
	/*
	 * When the PowerPC 83xx is powered on, the processor fetches the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

    lis     r4, HIADJ(start)                /* load r4 with the address */
    addi    r4, r4, LO(start)               /* of start */

    lis     r5, HIADJ(romInit)              /* load r5 with the address */
    addi    r5, r5, LO(romInit)             /* of romInit() */

    lis     r6, HIADJ(ROM_TEXT_ADRS)        /* load r6 with the address */
    addi    r6, r6, LO(ROM_TEXT_ADRS)       /* of ROM_TEXT_ADRS */

    sub     r4, r4, r5                      /*  */
    add     r4, r4, r6

    mtspr   LR, r4                          /* save destination address*/
                                            /* into LR register */
    blr                                     /* jump to flash mem address */
start:

	/* set the MSR register to a known state */

	xor	r0, r0, r0		/* clear register R0 */
	isync				/* synchronize */
	mtmsr 	r0			/* clear the MSR register */
	sync
	isync				/* synchronize */


	WRITEADR(r6,r7,QUICC_BR0(CCSBAR),FLASH_BASE_ADRS|0x1001)
	
	WRITEADR(r6,r7,QUICC_OR0(CCSBAR),FLASH_BASE_ADRS|0x0FF7) 


#ifdef BMS_HIGH_ENABLE

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,0), 0x00000000)
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,0), 0x00000000)
		
	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,0))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,0))
	lwz  r7,0(r6)
	
#else
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,0), FLASH_BASE_ADRS)
	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,0), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_8MB ))

	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,0))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,0))
	lwz  r7,0(r6)
	
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,1), FLASH_BASE_ADRS)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,1), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_32MB ) )

	
	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,1))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,1))
	lwz  r7,0(r6)
	isync
#endif
	WRITEADR(r6,r7, M83XX_SICRL(CCSBAR),0x80000000)
	isync
	WRITEADR(r6,r7, M83XX_SICRH(CCSBAR),0x00000002)
	isync
    /* disable clocks, peripheral driver or sysHwInit() will start  */
    WRITEADR(r6,r7, QUICC_LBCR(CCSBAR),0)
	isync
	
	
	/* Initialise the Local Bus Controller */
	WRITEADR(r6,r7,QUICC_LCRR(CCSBAR),0x80000004) 

	
	li  r6,0x0020
	mtctr r6
lbcdelay:
	nop
	bdnz lbcdelay
	nop
	isync
	sync
	
	mtspr   1008, r0        /* HID0 */
    isync
	
         /* Zero-out registers: SPRGs */
 
	addis    r0,0,0
	isync				/* synchronize */

    mtspr   272,r0
    mtspr   273,r0
    mtspr   274,r0
    mtspr   275,r0
	isync				/* synchronize */

    /* zero-out the Segment registers */

    mtsr    0,r0
    isync
    mtsr    1,r0
    isync
    mtsr    2,r0
    isync
    mtsr    3,r0
    isync
    mtsr    4,r0
    isync
    mtsr    5,r0
    isync
    mtsr    6,r0
    isync
    mtsr    7,r0
    isync
    mtsr    8,r0
    isync
    mtsr    9,r0
    isync
    mtsr    10,r0
    isync
    mtsr    11,r0
    isync
    mtsr    12,r0
    isync
    mtsr    13,r0
    isync
    mtsr    14,r0
    isync
    mtsr    15,r0
    isync
 
	/* invalidate DBATs: clear VP and VS bits */

	mtspr   536,r0   /* Data bat register 0 upper */
	isync
	mtspr   538,r0   /* Data bat register 1 upper */
	isync
	mtspr   540,r0   /* Data bat register 2 upper */
	isync
	mtspr   542,r0   /* Data bat register 3 upper */
	isync
	
	/* invalidate IBATs: clear VP and VS bits */

	mtspr   528,r0   /* Instruction bat register 0 upper */
	isync
	mtspr   530,r0   /* Instruction bat register 1 upper */
	isync
	mtspr   532,r0   /* Instruction bat register 2 upper */
	isync
	mtspr   534,r0   /* Instruction bat register 3 upper */
	isync

	/* invalidate TLBs: loop on all TLB entries using r7 as an index */

	addi     r0,0,0x0020
	mtspr    9,r0			/* Load CTR with 32 */
	addi     r7,0,0            	/* Use r7 as the tlb index */
 
tlb_write_loop:
 
	tlbie    r7                	/* invalidate the tlb entry */
	sync
	addi     r7,r7,0x1000          	/* increment the index */
	bc       16,0,tlb_write_loop   	/* Decrement CTR, then branch if the */
				       	/* decremented CTR is not equal to 0 */

    /* Turn off data and instruction cache control bits */

    mfspr   r7, HID0
    isync
	sync				/* synchronize */
	andi.	r7,r7,0x3FFF   		/* Clear DCE and ICE bits */
	mtspr	HID0,r7
    isync
	sync				/* synchronize */

#if 0
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,0), (BCSR_BASE_ADRS))

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,0), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_32KB ))
	
	WRITEADR(r6,r7,QUICC_OR1 (CCSBAR), \
		 (BCSR_BASE_ADRS & 0xffff0000) | 0xe9f7)

	/* load BR2 */
	WRITEADR(r6,r7,QUICC_BR1 (CCSBAR), 0xffff0801)
	
	isync
	sync
#endif

#ifndef BOOT_FROM_UBOOT
#ifdef INCLUDE_DDR_SDRAM
	/* Memory mapped region base address */
	
	WRITEADR(r6,r7,M83XX_DDRLAWBARn(CCSBAR,0), \
		 DDR_SDRAM_LOCAL_ADRS)
	 
	WRITEADR(r6,r7,M83XX_DDRLAWARn(CCSBAR,0), \
		 LAWAR_ENABLE  | LAWAR_SIZE_512MB ) 

	nop
	nop
	nop
	nop
	isync
		
		
	/* Initialize the DDR Memory controller */
        lis	r6, HI(DDRBA)
        ori	r6, r6, LO(DDRBA)		/* r6 = DDR base */
	WRITEOFFSET(r6,r7,(CS0_BNDS), 0x0000001f)
	WRITEOFFSET(r6,r7,(CS1_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS2_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS3_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS0_CONFIG), 0x80014102)
	WRITEOFFSET(r6,r7,(CS1_CONFIG), 0x00000000)
	WRITEOFFSET(r6,r7,(CS2_CONFIG), 0x00000000)
	WRITEOFFSET(r6,r7,(CS3_CONFIG), 0x00000000)
	WRITEOFFSET(r6,r7,(TIMING_CFG_0), 0x00220802)
	WRITEOFFSET(r6,r7,(TIMING_CFG_1), 0x3935D322)
	WRITEOFFSET(r6,r7,(TIMING_CFG_2), 0x231048C8)
	WRITEOFFSET(r6,r7,(TIMING_CFG_3), 0x00000000)

	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0x43000000)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG_2), 0x00001000)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_MODE_CFG), 0x44500632)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_MODE_CFG_2), 0x8000c000)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_INTERVAL), 0x03CF0080)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CLK_CNTRL), 0x02000000)
	lis  r7,0x0001
	mtctr r7
delayddr1:
	nop
	bdnz delayddr1

	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0xc3000000) 
	sync
	isync
	
	lis  r7,0x0001
	mtctr r7
delayddr2:
	nop
	bdnz delayddr2
	isync
	sync
	
#endif /* INCLUDE_DDR_SDRAM */
#endif

	isync

	bl sysClearFPRegs

warm:
	/* turn the instruction cache ON for faster FLASH ROM boots */
	mfspr   r4, HID0
	ori	r4, r4, _PPC_HID0_ICE | _PPC_HID0_ICFI	/* set ICE & ICFI */
	rlwinm	r5, r4, 0, _PPC_HID0_BIT_ICFI + 1, _PPC_HID0_BIT_ICFI - 1
				/* clear the ICFI bit */
	isync

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	mtspr	HID0, r4	/* Enable Instr Cache & Inval cache */
	sync
	mtspr	HID0, r5	/* using 2 consec instructions */
				/* E300 core recommendation */
    isync                                
        
        /* initialize the stack pointer */

	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	
	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

    lis     r7, HIADJ(romInit)
    addi    r7, r7, LO(romInit)

    lis     r8, HIADJ(ROM_TEXT_ADRS)
    addi    r8, r8, LO(ROM_TEXT_ADRS)

    lis	r6, HIADJ(romStart)	
    addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */
	mr      r3, r11
	mtspr	LR, r6				/* save destination address*/
						/* into LR register */
	blr				/* jump to the C entry point */