📄 sys8379.v
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module sys8379(
inout [0:7] LBD,
input [26:28]LBA,
input nHRESET,
input nPORESET_811,
output nPORESET,
output nFHRESET,
input nLCS0,
input nLCS1,
input nBOOT1, input CFG_CLKIN_DIV,
input PCI_HOST_nAGENT,
/*CFG_RESET_SOURCE[0:2]*/
inout SRC0,
inout SRC1,
inout SRC2,
/*CFG_CLKIN_DIV*/
inout SRC3,
inout MDC,
output nF0CS,
output nNAND_CS1,
input nLGPL2,
output nLBGPL2,
input nLWE0,
output nLBWE0,
input nRSTIN,
output nRSTOUT
);
parameter LRCW_BYTE_0=8'h26,
LRCW_BYTE_1=8'h03,
LRCW_BYTE_2=8'h00,
LRCW_BYTE_3=8'h00,
HRCW_BYTE_0=8'ha4,
HRCW_BYTE_1=8'h60,
HRCW_BYTE_2=8'h6c,
HRCW_BYTE_3=8'h02;
wire cs0_out;
reg [7:0] dataOut0;
assign cs0_out=(nHRESET)? nLCS0:1'b1;
assign nF0CS=cs0_out;
assign nNAND_CS1=nLCS1;
// reset configurate word
unibustri8 unibustri8_cs0(
.data (dataOut0),
.enabledt ((~nLCS0)& (~nHRESET)),
.tridata ( LBD[0:7] )
);
always @(*)
begin
case (LBA[26:28])
3'b000:
dataOut0[7:0]=LRCW_BYTE_0;
3'b001:
dataOut0[7:0]=LRCW_BYTE_1;
3'b010:
dataOut0[7:0]=LRCW_BYTE_2;
3'b011:
dataOut0[7:0]=LRCW_BYTE_3;
3'b100:
dataOut0[7:0]=HRCW_BYTE_0;
3'b101:
dataOut0[7:0]=HRCW_BYTE_1;
3'b110:
dataOut0[7:0]=HRCW_BYTE_2;
3'b111:
dataOut0[7:0]=HRCW_BYTE_3;
endcase
end
unibustri5 unibustri5_inst (
.data ( {4'b0,CFG_CLKIN_DIV}),
.enabledt ( ~nHRESET ),
.tridata ( {SRC0,SRC1,SRC2,SRC3,MDC})
);
assign nPORESET= nPORESET_811;
assign nRSTOUT= nHRESET;
assign nFHRESET = nHRESET;
assign nLBWE0 =nLWE0;
assign nLBGPL2 =nLGPL2;
endmodule
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