at91_serial_fixup.h

AT91SAM9260usart485功能的使能驱动

#define AT91C_PB21_RXD1		(AT91C_PIO_PB21) //  USART 1 Receive Data
#define AT91C_PIO_PB22		(1 << 22)
#define AT91C_PB22_SCK1		(AT91C_PIO_PB22) //  USART 1 Serial Clock
#define AT91C_PIO_PB23		(1 << 23)
#define AT91C_PB23_DCD1		(AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
#define AT91C_PIO_PB24		(1 << 24)
#define AT91C_PB24_CTS1		(AT91C_PIO_PB24) //  USART 1 Clear To Send
#define AT91C_PIO_PB25		(1 << 25)
#define AT91C_PB25_DSR1		(AT91C_PIO_PB25) //  USART 1 Data Set ready
#define AT91C_PB25_EF100	(AT91C_PIO_PB25) //  Ethernet MAC Force 100 Mbits/sec
#define AT91C_PIO_PB26		(1 << 26)
#define AT91C_PB26_RTS1		(AT91C_PIO_PB26) //  USART 1 Ready To Send
#define AT91C_PIO_PB27		(1 << 27)
#define AT91C_PB27_PCK0		(AT91C_PIO_PB27) //  PMC Programmable Clock Output 0
#define AT91C_PIO_PB28		(1 << 28)
#define AT91C_PB28_FIQ		(AT91C_PIO_PB28) //  AIC Fast Interrupt Input
#define AT91C_PIO_PB29		(1 << 29)
#define AT91C_PB29_IRQ0		(AT91C_PIO_PB29) //  Interrupt input 0

#define AT91C_PIO_PC0		(1 <<  0)
#define AT91C_PC0_BFCK		(AT91C_PIO_PC0) //  Burst Flash Clock
#define AT91C_PIO_PC1		(1 <<  1)
#define AT91C_PC1_BFRDY_SMOE	(AT91C_PIO_PC1) //  Burst Flash Ready
#define AT91C_PIO_PC2		(1 <<  2)
#define AT91C_PC2_BFAVD		(AT91C_PIO_PC2) //  Burst Flash Address Valid
#define AT91C_PIO_PC3		(1 <<  3)
#define AT91C_PC3_BFBAA_SMWE	(AT91C_PIO_PC3) //  Burst Flash Address Advance / SmartMedia Write Enable
#define AT91C_PIO_PC4		(1 <<  4)
#define AT91C_PC4_BFOE		(AT91C_PIO_PC4) //  Burst Flash Output Enable
#define AT91C_PIO_PC5		(1 <<  5)
#define AT91C_PC5_BFWE		(AT91C_PIO_PC5) //  Burst Flash Write Enable
#define AT91C_PIO_PC6		(1 <<  6)
#define AT91C_PC6_NWAIT		(AT91C_PIO_PC6) //  NWAIT
#define AT91C_PIO_PC7		(1 <<  7)
#define AT91C_PC7_A23		(AT91C_PIO_PC7) //  Address Bus[23]
#define AT91C_PIO_PC8		(1 <<  8)
#define AT91C_PC8_A24		(AT91C_PIO_PC8) //  Address Bus[24]
#define AT91C_PIO_PC9		(1 <<  9)
#define AT91C_PC9_A25_CFRNW	(AT91C_PIO_PC9) //  Address Bus[25] /  Compact Flash Read Not Write
#define AT91C_PIO_PC10		(1 << 10)
#define AT91C_PC10_NCS4_CFCS	(AT91C_PIO_PC10) //  Compact Flash Chip Select
#define AT91C_PIO_PC11		(1 << 11)
#define AT91C_PC11_NCS5_CFCE1	(AT91C_PIO_PC11) //  Chip Select 5 / Compact Flash Chip Enable 1
#define AT91C_PIO_PC12		(1 << 12)
#define AT91C_PC12_NCS6_CFCE2	(AT91C_PIO_PC12) //  Chip Select 6 / Compact Flash Chip Enable 2
#define AT91C_PIO_PC13		(1 << 13)
#define AT91C_PC13_NCS7		(AT91C_PIO_PC13) //  Chip Select 7
#define AT91C_PIO_PC14		(1 << 14)
#define AT91C_PIO_PC15		(1 << 15)
#define AT91C_PIO_PC16		(1 << 16)
#define AT91C_PC16_D16		(AT91C_PIO_PC16) //  Data Bus [16]
#define AT91C_PIO_PC17		(1 << 17)
#define AT91C_PC17_D17		(AT91C_PIO_PC17) //  Data Bus [17]
#define AT91C_PIO_PC18		(1 << 18)
#define AT91C_PC18_D18		(AT91C_PIO_PC18) //  Data Bus [18]
#define AT91C_PIO_PC19		(1 << 19)
#define AT91C_PC19_D19		(AT91C_PIO_PC19) //  Data Bus [19]
#define AT91C_PIO_PC20		(1 << 20)
#define AT91C_PC20_D20		(AT91C_PIO_PC20) //  Data Bus [20]
#define AT91C_PIO_PC21		(1 << 21)
#define AT91C_PC21_D21		(AT91C_PIO_PC21) //  Data Bus [21]
#define AT91C_PIO_PC22		(1 << 22)
#define AT91C_PC22_D22		(AT91C_PIO_PC22) //  Data Bus [22]
#define AT91C_PIO_PC23		(1 << 23)
#define AT91C_PC23_D23		(AT91C_PIO_PC23) //  Data Bus [23]
#define AT91C_PIO_PC24		(1 << 24)
#define AT91C_PC24_D24		(AT91C_PIO_PC24) //  Data Bus [24]
#define AT91C_PIO_PC25		(1 << 25)
#define AT91C_PC25_D25		(AT91C_PIO_PC25) //  Data Bus [25]
#define AT91C_PIO_PC26		(1 << 26)
#define AT91C_PC26_D26		(AT91C_PIO_PC26) //  Data Bus [26]
#define AT91C_PIO_PC27		(1 << 27)
#define AT91C_PC27_D27		(AT91C_PIO_PC27) //  Data Bus [27]
#define AT91C_PIO_PC28		(1 << 28)
#define AT91C_PC28_D28		(AT91C_PIO_PC28) //  Data Bus [28]
#define AT91C_PIO_PC29		(1 << 29)
#define AT91C_PC29_D29		(AT91C_PIO_PC29) //  Data Bus [29]
#define AT91C_PIO_PC30		(1 << 30)
#define AT91C_PC30_D30		(AT91C_PIO_PC30) //  Data Bus [30]
#define AT91C_PIO_PC31		(1 << 31)
#define AT91C_PC31_D31		(AT91C_PIO_PC31) //  Data Bus [31]

#define AT91C_PIO_PD0		(1 <<  0)
#define AT91C_PD0_ETX0		(AT91C_PIO_PD0) //  Ethernet MAC Transmit Data 0
#define AT91C_PIO_PD1		(1 <<  1)
#define AT91C_PD1_ETX1		(AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1
#define AT91C_PIO_PD2		(1 <<  2)
#define AT91C_PD2_ETX2		(AT91C_PIO_PD2) //  Ethernet MAC Transmit Data 2
#define AT91C_PIO_PD3		(1 <<  3)
#define AT91C_PD3_ETX3		(AT91C_PIO_PD3) //  Ethernet MAC Transmit Data 3
#define AT91C_PIO_PD4		(1 <<  4)
#define AT91C_PD4_ETXEN		(AT91C_PIO_PD4) //  Ethernet MAC Transmit Enable
#define AT91C_PIO_PD5		(1 <<  5)
#define AT91C_PD5_ETXER		(AT91C_PIO_PD5) //  Ethernet MAC Transmit Coding Error
#define AT91C_PIO_PD6		(1 <<  6)
#define AT91C_PD6_DTXD		(AT91C_PIO_PD6) //  DBGU Debug Transmit Data
#define AT91C_PIO_PD7		(1 <<  7)
#define AT91C_PD7_PCK0		(AT91C_PIO_PD7) //  PMC Programmable Clock Output 0
#define AT91C_PD7_TSYNC		(AT91C_PIO_PD7) //  ETM Synchronization signal
#define AT91C_PIO_PD8		(1 <<  8)
#define AT91C_PD8_PCK1		(AT91C_PIO_PD8) //  PMC Programmable Clock Output 1
#define AT91C_PD8_TCLK		(AT91C_PIO_PD8) //  ETM Trace Clock signal
#define AT91C_PIO_PD9		(1 <<  9)
#define AT91C_PD9_PCK2		(AT91C_PIO_PD9) //  PMC Programmable Clock 2
#define AT91C_PD9_TPS0		(AT91C_PIO_PD9) //  ETM ARM9 pipeline status 0
#define AT91C_PIO_PD10		(1 << 10)
#define AT91C_PD10_PCK3		(AT91C_PIO_PD10) //  PMC Programmable Clock Output 3
#define AT91C_PD10_TPS1		(AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1
#define AT91C_PIO_PD11		(1 << 11)
#define AT91C_PD11_TPS2		(AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2
#define AT91C_PIO_PD12		(1 << 12)
#define AT91C_PD12_TPK0		(AT91C_PIO_PD12) //  ETM Trace Packet 0
#define AT91C_PIO_PD13		(1 << 13)
#define AT91C_PD13_TPK1		(AT91C_PIO_PD13) //  ETM Trace Packet 1
#define AT91C_PIO_PD14		(1 << 14)
#define AT91C_PD14_TPK2		(AT91C_PIO_PD14) //  ETM Trace Packet 2
#define AT91C_PIO_PD15		(1 << 15)
#define AT91C_PD15_TD0		(AT91C_PIO_PD15) //  SSC Transmit data
#define AT91C_PD15_TPK3		(AT91C_PIO_PD15) //  ETM Trace Packet 3
#define AT91C_PIO_PD16		(1 << 16)
#define AT91C_PD16_TD1		(AT91C_PIO_PD16) //  SSC Transmit Data 1
#define AT91C_PD16_TPK4		(AT91C_PIO_PD16) //  ETM Trace Packet 4
#define AT91C_PIO_PD17		(1 << 17)
#define AT91C_PD17_TD2		(AT91C_PIO_PD17) //  SSC Transmit Data 2
#define AT91C_PD17_TPK5		(AT91C_PIO_PD17) //  ETM Trace Packet 5
#define AT91C_PIO_PD18		(1 << 18)
#define AT91C_PD18_NPCS1	(AT91C_PIO_PD18) //  SPI Peripheral Chip Select 1
#define AT91C_PD18_TPK6		(AT91C_PIO_PD18) //  ETM Trace Packet 6
#define AT91C_PIO_PD19		(1 << 19)
#define AT91C_PD19_NPCS2	(AT91C_PIO_PD19) //  SPI Peripheral Chip Select 2
#define AT91C_PD19_TPK7		(AT91C_PIO_PD19) //  ETM Trace Packet 7
#define AT91C_PIO_PD20		(1 << 20)
#define AT91C_PD20_NPCS3	(AT91C_PIO_PD20) //  SPI Peripheral Chip Select 3
#define AT91C_PD20_TPK8		(AT91C_PIO_PD20) //  ETM Trace Packet 8
#define AT91C_PIO_PD21		(1 << 21)
#define AT91C_PD21_RTS0		(AT91C_PIO_PD21) //  Usart 0 Ready To Send
#define AT91C_PD21_TPK9		(AT91C_PIO_PD21) //  ETM Trace Packet 9
#define AT91C_PIO_PD22		(1 << 22)
#define AT91C_PD22_RTS1		(AT91C_PIO_PD22) //  Usart 0 Ready To Send
#define AT91C_PD22_TPK10	(AT91C_PIO_PD22) //  ETM Trace Packet 10
#define AT91C_PIO_PD23		(1 << 23)
#define AT91C_PD23_RTS2		(AT91C_PIO_PD23) //  USART 2 Ready To Send
#define AT91C_PD23_TPK11	(AT91C_PIO_PD23) //  ETM Trace Packet 11
#define AT91C_PIO_PD24		(1 << 24)
#define AT91C_PD24_RTS3		(AT91C_PIO_PD24) //  USART 3 Ready To Send
#define AT91C_PD24_TPK12	(AT91C_PIO_PD24) //  ETM Trace Packet 12
#define AT91C_PIO_PD25		(1 << 25)
#define AT91C_PD25_DTR1		(AT91C_PIO_PD25) //  USART 1 Data Terminal ready
#define AT91C_PD25_TPK13	(AT91C_PIO_PD25) //  ETM Trace Packet 13
#define AT91C_PIO_PD26		(1 << 26)
#define AT91C_PD26_TPK14	(AT91C_PIO_PD26) //  ETM Trace Packet 14
#define AT91C_PIO_PD27		(1 << 27)
#define AT91C_PD27_TPK15	(AT91C_PIO_PD27) //  ETM Trace Packet 15

#define AT91C_US_USMODE       ( 0xF <<  0) // (USART) Usart mode
#define 	AT91C_US_USMODE_NORMAL               ( 0x0) // (USART) Normal
#define 	AT91C_US_USMODE_RS485                ( 0x1) // (USART) RS485
#define 	AT91C_US_USMODE_HWHSH                ( 0x2) // (USART) Hardware Handshaking
#define 	AT91C_US_USMODE_MODEM                ( 0x3) // (USART) Modem
#define 	AT91C_US_USMODE_ISO7816_0            ( 0x4) // (USART) ISO7816 protocol: T = 0
#define 	AT91C_US_USMODE_ISO7816_1            ( 0x6) // (USART) ISO7816 protocol: T = 1
#define 	AT91C_US_USMODE_IRDA                 ( 0x8) // (USART) IrDA
#define 	AT91C_US_USMODE_SWHSH                ( 0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS         ( 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define 	AT91C_US_CLKS_CLOCK                ( 0x0 <<  4) // (USART) Clock
#define 	AT91C_US_CLKS_FDIV1                ( 0x1 <<  4) // (USART) fdiv1
#define 	AT91C_US_CLKS_SLOW                 ( 0x2 <<  4) // (USART) slow_clock (ARM)
#define 	AT91C_US_CLKS_EXT                  ( 0x3 <<  4) // (USART) External (SCK)
#define AT91C_US_CHRL         ( 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define 	AT91C_US_CHRL_5_BITS               ( 0x0 <<  6) // (USART) Character Length: 5 bits
#define 	AT91C_US_CHRL_6_BITS               ( 0x1 <<  6) // (USART) Character Length: 6 bits
#define 	AT91C_US_CHRL_7_BITS               ( 0x2 <<  6) // (USART) Character Length: 7 bits
#define 	AT91C_US_CHRL_8_BITS               ( 0x3 <<  6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC         ( 0x1 <<  8) // (USART) Synchronous Mode Select
#define AT91C_US_PAR          ( 0x7 <<  9) // (USART) Parity type
#define		AT91C_US_PAR_EVEN                 ( 0x0 <<  9) // (USART) Even Parity
#define		AT91C_US_PAR_ODD                  ( 0x1 <<  9) // (USART) Odd Parity
#define 	AT91C_US_PAR_SPACE                ( 0x2 <<  9) // (USART) Parity forced to 0 (Space)
#define		AT91C_US_PAR_MARK                 ( 0x3 <<  9) // (USART) Parity forced to 1 (Mark)
#define		AT91C_US_PAR_NONE                 ( 0x4 <<  9) // (USART) No Parity
#define		AT91C_US_PAR_MULTI_DROP           ( 0x6 <<  9) // (USART) Multi-drop mode
#define AT91C_US_NBSTOP       ( 0x3 << 12) // (USART) Number of Stop bits
#define 	AT91C_US_NBSTOP_1_BIT                ( 0x0 << 12) // (USART) 1 stop bit
#define 	AT91C_US_NBSTOP_15_BIT               ( 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define 	AT91C_US_NBSTOP_2_BIT                ( 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_CHMODE       ( 0x3 << 14) // (USART) Channel Mode
#define 	AT91C_US_CHMODE_NORMAL               ( 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
#define 	AT91C_US_CHMODE_AUTO                 ( 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define 	AT91C_US_CHMODE_LOCAL                ( 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define 	AT91C_US_CHMODE_REMOTE               ( 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
#define AT91C_US_MSBF         ( 0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9        ( 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO         ( 0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER         ( 0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK        ( 0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK       ( 0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER     ( 0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER       ( 0x1 << 28) // (USART) Receive Line Filter


#endif