ports.lst

Oh, yes..... Asssssssm :-]]]]]]

		       bit 7   = 1     Typematic Rate Programming
		       bit 6-5 = 00    Typematic Rate Delay 250 mSec
		       bit 4-0 = 00011 Typematic Rate 21.8 Chars/Sec
		12    fixed disk drive type for drive 0 and drive 1
		       bit 7-4	drive type of drive 0
		       bit 3-0	drive type of drive 1
				if either of the nibbles equals 0F, then bytes
				19 an 1A are valid
		13    reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
		       bit 7 = 1  Mouse Support Option
		       bit 6 = 1  Above 1 MB Memory Test disable
		       bit 5 = 1  Memory Test Tick Sound disable
		       bit 4 = 1  Memory Parity Error Check enable
		       bit 3 = 1  Hit <ESC> Message Display disabled
		       bit 2 = 1  Hard Disk Type 47 Data Area at address 0:300
		       bit 1 = 1  Wait For <F1> If Any Error enabled
		       bit 0 = 1  System Boot Up Num Lock is On
		14    equipment byte
		       bit 7-6	 diskette drives installed
			       = 00  1 drive installed
			       = 01  2 drives installed
			       = 10  reserved
			       = 11  reserved
		       bit 5-4	 primary display
			       = 00  adapter card with option ROM 
			       = 01  40*25 color
			       = 10  80*25 color
			       = 11  monochrome
		       bit 3-2	 reserved
		       bit 1   = 1  coprocessor installed (non-Weitek)
		       bit 0	    diskette drive avaliable for boot
		15    LSB of systemn base memory in Kb
		16    MSB of systemn base memory in Kb
		17    LSB of total extended memory in Kb
		18    MSB of total extended memory in Kb
		19    drive C extension byte
		1A    drive D extension byte
		1B-27 reserved
		1B/1C word to 82335 RC1 roll compare register at [24]
			(Phoenix)
		1D/1E word to 82335 RC2 roll compare register at [26]
			(Phoenix)
		28    HP-Vectra checksum over 29-2D
		29-2D reserved
		29/2A word to Intel 82335 CC0 compare register at
			[28](Phoenix)
		2B/2C word send to 82335 CC1 compare register at [2A]
			(Phoenix)
		2D    AMI Extended CMOS setup (AMI Hi-Flex BIOS)
		      (Phoenix BIOS checks for the values AA or CC)
		       bit 7 = 1  Weitek Processor Absent
		       bit 6 = 1  Floppy Drive Seek At Boot disabled
		       bit 5 = 1  System Boot Up Sequence  C:, A:
		       bit 4 = 1  System Boot Up Speed is high
		       bit 3 = 1  Cache Memory enabled
		       bit 2 = 1  Internal Cache Memory	 <1>
		       bit 1-0	  reserved
		2E    CMOS MSB checksum over 10-2D
		2F    CMOS LSB checksum over 10-2D
		30    LSB of extended memory found above 1Mb at POST
		31    MSB of extended memory found above 1Mb at POST
		32    date century in BCD
		33    information flags
		       bit4 = bit4 from CPU register CR0   (Phoenix)
			      this bit is only known as INTEL RESERVED
		34-3F reserved	
		34     bit4 bit5 (Phoenix BIOS)
		3D/3E word to 82335 MCR memory config register at
			[22](Phoenix)
		3D     bit3	 base memsize 512/640  (Phoenix)
		3E     bit7 = 1	 relocate enable       (Phoenix)
		       bit1 = 1	 shadow video enable   (Phoenix)
		       bit0 = 1	 shadow BIOS enable    (Phoenix)


		User Definable Drive Parameters are also stored in CMOS RAM:

		AMI (386sx BIOS 1989) first user definable drive (type 47)
		 1B  L cylinders
		 1C  H cylinders
		 1D  heads
		 1E  L Write Precompensation Cylinder
		 1F  H Write Precompensation Cylinder
		 20  ??
		 21  L cylinders parking zone
		 22  H cylinders parking zone
		 23  sectors

		AMI (386sx BIOS 1989) second user definable drive (type 48)
		 24  L cylinders
		 25  H cylinders
		 26  heads
		 27  L Write Precompensation Cylinder
		 28  H Write Precompensation Cylinder
		 29  ??
		 2A  L cylinders parking zone
		 2B  H cylinders parking zone
		 2C  sectors

		Phoenix (386BIOS v1.10.03 1988) 1st user definable drv (type48)
		 20  L cylinders
		 21  H cylinders
		 22  heads
		 23  L Write Precompensation Cylinder
		 24  H Write Precompensation Cylinder
		 25  L cylinders parking zone
		 26  H cylinders parking zone
		 27  sectors

		Phoenix (386BIOS v1.10.03 1988) 2nd user definable drv (type49)
		(when PS/2-style password option is not used)
		 35  L cylinders
		 36  H cylinders
		 37  heads
		 38  L Write Precompensation Cylinder
		 39  H Write Precompensation Cylinder
		 3A  L cylinders parking zone
		 3B  H cylinders parking zone
		 3C  sectors

- - - - - - - - ---------------------------------------------------------------
0073	  ----	Intel Pentium motherboard ("Neptune" chipset)

0073	r/w	bit 7: ???

- - - - - - - - ---------------------------------------------------------------
0074-0076	secondary CMOS (Compaq)

0074	w	secondary CMOS RAM index (Compaq)

0076	r/w	secondary CMOS RAM (Compaq)

- - - - - - - - ---------------------------------------------------------------
0078		HP-Vectra  Hard Reset: NMI enable/disable
		 bit 7 = 0  disable & clear hard reset from HP-HIL controller
		       = 1  enable hard reset from HP-HIL controller chip
		 bit 6-0    reserved

-------------------------------------------------------------------------------
0078-007F ----	PC radio by CoZet Info Systems
		The I/O address range is dipswitch selectable from:
		   038-03F and 0B0-0BF
		   078-07F and 0F0-0FF
		   138-13F and 1B0-1BF
		   178-17F and 1F0-1FF
		   238-23F and 2B0-2BF
		   278-27F and 2F0-2FF
		   338-33F and 3B0-3BF
		   378-37F and 3F0-3FF
		All of these addresses show a readout of FF in initial state.
		Once started, all of the addresses show	 FB, whatever might
		happen.

-------------------------------------------------------------------------------
007C-007D ----	HP-Vectra  PIC 3   (Programmable Interrupt Controller 8259)
		cascaded to first controller.
		used for keyboard and input device interface.
007C	r/w	HP-Vectra  PIC 3  see at 0020  PIC 1
007D	r/w	HP-Vectra  PIC 3  see at 0021  PIC 1

-------------------------------------------------------------------------------
0080	w	Manufacturing Diagnostics port

-------------------------------------------------------------------------------
0080-008F ----	DMA page registers   (74612)

0080	r/w	extra page register (temporary storage)
0081	r/w	DMA channel 2 address byte 2
0082	r/w	DMA channel 3 address byte 2
0083	r/w	DMA channel 1 address byte 2
0084	r/w	extra page register
0085	r/w	extra page register
0086	r/w	extra page register
0087	r/w	DMA channel 0 address byte 2
0088	r/w	extra page register
0089	r/w	DMA channel 6 address byte 2
0089	r/w	DMA channel 7 address byte 2
0089	r/w	DMA channel 5 address byte 2
008C	r/w	extra page register
008D	r/w	extra page register
008E	r/w	extra page register
008F	r/w	DMA refresh page register

-------------------------------------------------------------------------------
0084	  ----	Compaq POST Diagnostic

-------------------------------------------------------------------------------
0084	  ----	EISA Synchronize Bus Cycle

-------------------------------------------------------------------------------
0090-009F ----	PS/2 POS (Programmable Option Select)

0090		Central arbitration control port
0091	r	Card selection feedback

0092	r/w	PS/2 system control port A  (port B is at 0061)
		 bit 7-6   any bit set to 1 turns activity light on
		 bit 5	   reserved
		 bit 4 = 1 watchdog timout occurred 
		 bit 3 = 0 RTC/CMOS security lock (on password area) unlocked
		       = 1 CMOS locked (done by POST)
		 bit 2	   reserved
		 bit 1 = 1 indicates A20 active
		 bit 0 = 0 system reset or write
			 1 pulse alternate reset pin (alternate CPU reset)

0094	w	system board enable/setup register
		 bit 7 = 1  enable functions
		       = 0  setup functions
		 bit 5 = 1  enables VGA
		       = 0  setup VGA

0095		reserved

0096	w	adapter enable /setup register
		 bit 3 = 1  setup adapters
		       = 0  enable registers

0097		reserved

-------------------------------------------------------------------------------
00A0-00AF ----	PIC 2	(Programmable Interrupt Controller 8259)

00A0	r/w	NMI mask register (XT)

00A0	r/w	PIC 2  same as 0020 for PIC 1
00A1	r/w	PIC 2  same as 0021 for PIC 1 except for OCW1:
		 bit 7 = 0  reserved
		 bit 6 = 0  enable fixed disk interrupt
		 bit 5 = 0  enable coprocessor exception interrupt
		 bit 4 = 0  enable mouse interrupt
		 bit 3 = 0  reserved
		 bit 2 = 0  reserved
		 bit 1 = 0  enable redirect cascade
		 bit 0 = 0  enable real-time clock interrupt

-------------------------------------------------------------------------------
00B0-00BF ----	PC radio by CoZet Info Systems
		The I/O address range is dipswitch selectable from:
		   038-03F and 0B0-0BF
		   078-07F and 0F0-0FF
		   138-13F and 1B0-1BF
		   178-17F and 1F0-1FF
		   238-23F and 2B0-2BF
		   278-27F and 2F0-2FF
		   338-33F and 3B0-3BF
		   378-37F and 3F0-3FF
		All of these addresses show a readout of FF in initial state.
		Once started, all of the addresses show	 FB, whatever might
		happen.

-------------------------------------------------------------------------------
00C0	  ----	TI  SN746496 programmable tone/noise generator	PCjr

-------------------------------------------------------------------------------
00C0-00DF ----	DMA 2	(second Direct Memory Access controller 8237)

00C0	r/w	DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2	r/w	DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4	r/w	DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6	r/w	DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8	r/w	DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA	r/w	DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC	r/w	DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE	r/w	DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0	r	DMA channel 4-7 status register (ISA, EISA)
		 bit 7 = 1  channel 7 request
		 bit 6 = 1  channel 6 request
		 bit 5 = 1  channel 5 request
		 bit 4 = 1  channel 4 request
		 bit 3 = 1  terminal count on channel 7
		 bit 2 = 1  terminal count on channel 6
		 bit 1 = 1  terminal count on channel 5
		 bit 0 = 1  terminal count on channel 4

00D0	w	DMA channel 4-7 command register (ISA, EISA)
		 bit 7 = 1  DACK sense active high
		       = 0  DACK sense active low
		 bit 6 = 1  DREQ sense active high
		       = 0  DREQ sense active low
		 bit 5 = 1  extended write selection
		       = 0  late write selection
		 bit 4 = 1  rotating priority
		       = 0  fixed priority
		 bit 3 = 1  compressed timing
		       = 0  normal timing
		 bit 2 = 0  enable controller
		 bit 1 = 1  enable memory-to-memory transfer
		 bit 0	    .....

00D2	w	DMA channel 4-7 write request register (ISA, EISA)

00D4	w	DMA channel 4-7 write single mask register (ISA, EISA)
		 bit 7-3      reserved
		 bit 2	 = 0  clear mask bit
			 = 1  set mask bit
		 bit 1-0 = 00 channel 4 select
			 = 01 channel 5 select
			 = 10 channel 6 select
			 = 11 channel 7 select

00D6	w	DMA channel 4-7 mode register (ISA, EISA)
		 bit 7-6 = 00  demand mode
			 = 01  single mode
			 = 10  block mode
			 = 11  cascade mode
		 bit 5	 = 0   address increment select
			 = 1   address decrement select
		 bit 4	 = 0   autoinitialisation disable
			 = 1   autoinitialisation enable
		 bit 3-2 = 00  verify operation
			 = 01  write to memory
			 = 10  read from memory
			 = 11  reserved
		 bit 1-0 = 00  channel 4 select
			 = 01  channel 5 select
			 = 10  channel 6 select
			 = 11  channel 7 select

00D8	w	DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)
00DA	r	DMA channel 4-7 read temporary register (ISA, EISA)
00DA	w	DMA channel 4-7 master clear (ISA, EISA)
00DC	w	DMA channel 4-7 clear mask register (ISA, EISA)
00DE	w	DMA channel 4-7 write mask register (ISA, EISA)

-------------------------------------------------------------------------------
00E0-00E7 ----	Microchannel

00E0	r/w	split address register, memory encoding registers PS/2m80 only
00E1	r/w	memory register
00E3	r/w	error trace
00E4	r/w	error trace
00E5	r/w	error trace
00E7	r/w	error trace

-------------------------------------------------------------------------------
00F0-00F5 ----	PCjr Disk Controller

00F0		disk controller
00F2		disk controller control port
00F4		disk controller status register
00F5		disk controller data port

-------------------------------------------------------------------------------
00F0-00FF ----	coprocessor (8087..80387)

00F0	w	math coprocessor clear busy latch
00F1	w	math coprocessor reset
00F8	r/w	opcode transfer
00FA	r/w	opcode transfer
00FC	r/w	opcode transfer

-------------------------------------------------------------------------------
00F9-00FF ----	PC radio by CoZet Info Systems
		The I/O address range is dipswitch selectable from:
		   038-03F and 0B0-0BF
		   078-07F and 0F0-0FF
		   138-13F and 1B0-1BF
		   178-17F and 1F0-1FF
		   238-23F and 2B0-2BF