📄 ports.lst
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[This file was provided by Wim Osterholt (2:512/56 or wim@djo.wtm.tudelft.nl).]
Last Change: 11/6/94
XT, AT and PS/2 I/O port addresses
Do NOT consider this information as complete and accurate.
If you want to do harware programming check ALWAYS the
appropriate data sheets. Be aware that erroneously programming
can put your hardware or your data at risk.
There is a memory mapped address in use for I/O functions of which I
think it should be mentioned here. See at the end of this list.
-------------------------------------------------------------------------------
0000-001F ---- DMA 1 (first Direct Memory Access controller 8237)
0000 r/w DMA channel 0 address byte 0, then byte 1.
0001 r/w DMA channel 0 word count byte 0, then byte 1.
0002 r/w DMA channel 1 address byte 0, then byte 1.
0003 r/w DMA channel 1 word count byte 0, then byte 1.
0004 r/w DMA channel 2 address byte 0, then byte 1.
0005 r/w DMA channel 2 word count byte 0, then byte 1.
0006 r/w DMA channel 3 address byte 0, then byte 1.
0007 r/w DMA channel 3 word count byte 0, then byte 1.
0008 r DMA channel 0-3 status register
bit 7 = 1 channel 3 request
bit 6 = 1 channel 2 request
bit 5 = 1 channel 1 request
bit 4 = 1 channel 0 request
bit 3 = 1 channel terminal count on channel 3
bit 2 = 1 channel terminal count on channel 2
bit 1 = 1 channel terminal count on channel 1
bit 0 = 1 channel terminal count on channel 0
0008 w DMA channel 0-3 command register
bit 7 = 1 DACK sense active high
= 0 DACK sense active low
bit 6 = 1 DREQ sense active high
= 0 DREQ sense active low
bit 5 = 1 extended write selection
= 0 late write selection
bit 4 = 1 rotating priority
= 0 fixed priority
bit 3 = 1 compressed timing
= 0 normal timing
bit 2 = 1 enable controller
= 0 enable memory-to-memory
0009 w DMA write request register
000A r/w DMA channel 0-3 mask register
bit 7-3 = 0 reserved
bit 2 = 0 clear mask bit
= 1 set mask bit
bit 1-0 = 00 channel 0 select
= 01 channel 1 select
= 10 channel 2 select
= 11 channel 3 select
000B w DMA channel 0-3 mode register
bit 7-6 = 00 demand mode
= 01 single mode
= 10 block mode
= 11 cascade mode
bit 5 = 0 address increment select
= 1 address decrement select
bit 3-2 = 00 verify operation
= 01 write to memory
= 10 read from memory
= 11 reserved
bit 1-0 = 00 channel 0 select
= 01 channel 1 select
= 10 channel 2 select
= 11 channel 3 select
000C w DMA clear byte pointer flip-flop
000D r DMA read temporary register
000D w DMA master clear
000E w DMA clear mask register
000F w DMA write mask register
-------------------------------------------------------------------------------
0010-001F ---- DMA controller (8237) on PS/2 model 60 & 80
-------------------------------------------------------------------------------
0018 w PS/2 extended function register
-------------------------------------------------------------------------------
001A PS/2 extended function execute
-------------------------------------------------------------------------------
0020-003F ---- PIC 1 (Programmable Interrupt Controller 8259)
0020 w PIC initialization command word ICW1
bit 7-5 = 0 only used in 80/85 mode
bit 4 = 1 ICW1 is being issued
bit 3 = 0 edge triggered mode
= 1 level triggered mode
bit 2 = 0 successive interrupt vectors use 8 bytes
= 1 successive interrupt vectors use 4 bytes
bit 1 = 0 cascade mode
= 1 single mode, no ICW3 needed
bit 0 = 0 no ICW4 needed
= 1 ICW4 needed
0021 w PIC ICW2,ICW3,ICW4 after ICW1 to 0020
ICW2:
bit 7-3 = address lines A0-A3 of base vector address for PIC
bit 2-0 = reserved
ICW3:
bit 7-0 = 0 slave controller not attached to corresponding
interrupt pin
= 1 slave controller attached to corresponding
interrupt pin
ICW4:
bit 7-5 = 0 reserved
bit 4 = 0 no special fully-nested mode
= 1 special fully-nested mode
bit 3-2 = 0x nonbuffered mode
= 10 buffered mode/slave
= 11 buffered mode/master
bit 1 = 0 normal EOI
= 1 Auto EOI
bit 0 = 0 8085 mode
= 1 8086/8088 mode
0021 r/w PIC master interrupt mask register
OCW1:
bit 7 = 0 enable parallel printer interrupt
bit 6 = 0 enable diskette interrupt
bit 5 = 0 enable fixed disk interrupt
bit 4 = 0 enable serial port 1 interrupt
bit 3 = 0 enable serial port 2 interrupt
bit 2 = 0 enable video interrupt
bit 1 = 0 enable keyboard, mouse, RTC interrupt
bit 0 = 0 enable timer interrupt
0020 r PIC interrupt request/in-service registers by OCW3
request register:
bit 7-0 = 0 no active request for the corresponding int. line
= 1 active request for corresponding interrupt line
in-service register:
bit 7-0 = 0 corresponding line not currently being serviced
= 1 corresponding int. line currently being serviced
0020 w OCW2:
bit 7-5 = 000 rotate in auto EOI mode (clear)
= 001 nonspecific EOI
= 010 no operation
= 011 specific EOI
= 100 rotate in auto EOI mode (set)
= 101 rotate on nonspecific EOI command
= 110 set priority command
= 111 rotate on specific EOI command
bit 4 = 0 reserved
bit 3 = 0 reserved
bit 2-0 interrupt request to which the command applies
0020 w PIC OCW3
bit 7 = 0 reserved
bit 6-5 = 0x no operation
= 10 reset special mask
= 11 set special mask
bit 4 = 0 reserved
bit 3 = 1 reserved
bit 2 = 0 no poll command
= 1 poll command
bit 1-0 = 0x no operation
= 10 read int.request register on next read at 0020
= 11 read int.in-service register on next read 0020
-------------------------------------------------------------------------------
0022-002B ---- Intel 82355, part of chipset for 386sx
initialisation in POST will disable these addresses,
only a hard reset will enable them again.
0022 r/w 82335 MCR memory configuration register
0024 82335 RC1 roll compare register
0026 82335 RC2 roll compare register
0028 82335 CC0 compare register
002A 82335 CC1 compare register
values for CC0 and CC1:
00F9,0000 enable range compare CC0 0-512K CC1 disable
00F1,0000 enable range compare CC0 0-1024K CC1 disable
00F1,10F9 enable range compare CC0 0-1M CC1 1M-1M5
00E1,0000 enable range compare CC0 0-2M CC1 disable
00E1,0000 enable range compare CC0 0-2M CC1 disable
00C1,0000 enable range compare CC0 0-4M CC1 disable
00C1,40E1 enable range compare CC0 0-4M CC1 4M-6M
0081,0000 enable range compare CC0 0-8M CC1 disable
-------------------------------------------------------------------------------
0022-0023 ---- Chip Set Data
0022 w index for accesses to data port
0023 r/w chip set data
-------------------------------------------------------------------------------
0022-0023 ---- Cyrix Cx486SLC/DLC processor Cache Configuration Registers
0022 w index for accesses to next port
C0h CR0
C1h CR1
C4h non-cacheable region 1, start address bits 31-24
C5h non-cacheable region 1, start address bits 23-16
C6h non-cacheable region 1, start addr 15-12, size (low nibble)
C7h non-cacheable region 2, start address bits 31-24
C8h non-cacheable region 2, start address bits 23-16
C9h non-cacheable region 2, start addr 15-12, size (low nibble)
CAh non-cacheable region 3, start address bits 31-24
CBh non-cacheable region 3, start address bits 23-16
CCh non-cacheable region 3, start addr 15-12, size (low nibble)
CDh non-cacheable region 4, start address bits 31-24
CEh non-cacheable region 4, start address bits 23-16
CFh non-cacheable region 4, start addr 15-12, size (low nibble)
0023 r/w cache configuration register array (indexed by port 0022h)
non-cacheable region sizes:
00h disabled
01h 4K
02h 8K
03h 16K
04h 32K
05h 64K
06h 128K
07h 256K
08h 512K
09h 1M
0Ah 2M
0Bh 4M
0Ch 8M
0Dh 16M
0Eh 32M
0Fh 4G
Configuration Register 0 format:
bit 0 "NC0" first 64K of each 1M noncacheable in real/V86
bit 1 "NC1" 640K-1M noncacheable
bit 2 "A20M" enables A20M# input pin
bit 3 "KEN" enables KEN# input pin
bit 4 "FLUSH" enables KEN# input pin
bit 5 "BARB" enables internal cache flushing on bus holds
bit 6 "C0" cache direct-mapped instead of 2-way associative
bit 7 "SUSPEND" enables SUSP# input and SUSPA# output pins
Configuration Register 1 format;
bit 0 "RPL" enables output pins RPLSET and RPLVAL#
-------------------------------------------------------------------------------
0026-0027 ---- Power Management
0026 w index for data port
0027 r/w power management data
-------------------------------------------------------------------------------
0038-003F ---- PC radio by CoZet Info Systems
The I/O address range is dipswitch selectable from:
038-03F and 0B0-0BF
078-07F and 0F0-0FF
138-13F and 1B0-1BF
178-17F and 1F0-1FF
238-23F and 2B0-2BF
278-27F and 2F0-2FF
338-33F and 3B0-3BF
378-37F and 3F0-3FF
All of these addresses show a readout of FF in initial state.
Once started, all of the addresses show FB, whatever might
happen.
-------------------------------------------------------------------------------
0040-005F ---- PIT (Programmable Interrupt Timer 8253, 8254)
XT & AT uses 40-43 PS/2 uses 40, 42,43,44, 47
0040 r/w PIT counter 0, counter divisor (XT, AT, PS/2)
0041 r/w PIT counter 1, RAM refresh counter (XT, AT)
0042 r/w PIT counter 2, cassette & speaker (XT, AT, PS/2)
0043 r/w PIT mode port, control word register for counters 0-2
bit 7-6 = 00 counter 0 select
= 01 counter 1 select (not PS/2)
= 10 counter 2 select
bit 5-4 = 00 counter latch command
= 01 read/write counter bits 0-7 only
= 10 read/write counter bits 8-15 only
= 11 read/write counter bits 0-7 first, then 8-15
bit 3-1 = 000 mode 0 select
= 001 mode 1 select - programmable one shot
= x10 mode 2 select - rate generator
= x11 mode 3 select - square wave generator
= 100 mode 4 select - software triggered strobe
= 101 mode 5 select - hardware triggered strobe
bit 0 = 0 binary counter 16 bits
= 1 BCD counter
0044 r/w PIT counter 3 (PS/2, EISA)
used as fail-safe timer. generates an NMI on time out.
for user generated NMI see at 0462.
0047 w PIT control word register counter 3 (PS/2, EISA)
bit 7-6 = 00 counter 3 select
= 01 reserved
= 10 reserved
= 11 reserved
bit 5-4 = 00 counter latch command counter 3
= 01 read/write counter bits 0-7 only
= 1x reserved
bit 3-0 = 00
0048 EISA
0049 8254 timer 2, not used (counter 1)
004A EISA programmable interval timer 2
004B EISA programmable interval timer 2
-------------------------------------------------------------------------------
0060-006F ---- Keyboard controller 804x (8041, 8042) (or PPI (8255) on PC,XT)
XT uses 60-63, AT uses 60-64
AT keyboard controller input port bit definitions
bit 7 = 0 keyboard inhibited
bit 6 = 0 CGA, else MDA
bit 5 = 0 manufacturing jumper installed
bit 4 = 0 system RAM 512K, else 640K
bit 3-0 reserved
AT keyboard controller input port bit definitions by Compaq
bit 7 = 0 security lock is locked
bit 6 = 0 Compaq dual-scan display, 1=non-Compaq display
bit 5 = 0 system board dip switch 5 is ON
bit 4 = 0 auto speed selected, 1=high speed selected
bit 3 = 0 slow (4MHz), 1 = fast (8MHz)
bit 2 = 0 80287 installed, 1= no NDP installed
bit 1-0 reserved
AT keyboard controller output port bit definitions
bit 7 = keyboard data output
bit 6 = keyboard clock output
bit 5 = 0 input buffer full
bit 4 = 0 output buffer empty
bit 3 = reserved (see note)
bit 2 = reserved (see note)
bit 1 = gate A20
bit 0 = system reset
Note: bits 2 and 3 are the turbo speed switch or password
lock on Award/AMI/Phoenix BIOSes. These bits make
use of nonstandard keyboard controller BIOS
functionality to manipulate
pin 23 (8041 port 22) as turbo switch for AWARD
pin 35 (8041 port 15) as turbo switch/pw lock for
Phoenix
0060 r/w KB controller data port or keyboard input buffer (ISA, EISA)
should only be read from after status port bit0 = 1
should only be written to if status port bit1 = 0
keyboard commands (data also goes to port 0060):
E6 sngl set mouse scaling to 1:1
E7 sngl set mouse scaling to 2:1
E8 dbl set mouse resolution
(00h = 1/mm,01h = 2/mm,02h = 4/mm,03h = 8/mm)
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