ports.c

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		bit 6: "SEND_SENSE"
		bit 5: "SEND_REJ"
		bits 4-0: reserved
 37h	WORD	channel A active targets (ACTIVE_A)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
 39h	BYTE	reserved
 3Ah	WORD	SCSI configuration (SCSICONF)
		bits 15-12: reserved?
		bits 11-8: (Wide SCSI) our ID (see #P0982)
		bit 7: (AIC-777x) enable SCSI low byte termination (see #P1011)
		bit 6: enable SCSI bus reset at power up (RESET_SCSI)
			 (see #P1011)
		bit 5: enable SCSI parity check (ENSPCHK) (see #P0980)
		bits 4-3: selection time-out select (STIMESEL) (see #P0980)
		bits 2-0: our ID (see #P0982)
 3Bh	BYTE	channel B SCSI configuration
		see bits 7-0 above
 3Ch	BYTE	"INTDEF"
		bits 7-4: reserved?
		bits 3-0: IRQ number (IRQ9..IRQ12, IRQ14, and IRQ15 are valid)
 3Dh	BYTE	host configuration (HOSTCONF)
		bits 7-6: DMA FIFO threshold (DFTHRSH) (see #9038)
		bits 5-2: bus off time (BOFF) (see #9037)
		bits 1-0: reserved?
 3Eh	BYTE	reserved
 3Fh	BYTE	(AIC-7771) BIOS control (BIOSCTRL)
		bits 5-4: BIOS mode (BIOSMODE)
			  11 BIOS disabled (BIOSDISABLED)
		bit 3: channel B is primary (CHANNEL_B_PRIMARY)
Notes:	the scratch RAM is used for passing information between the driver and
	  BIOS and the code running on the PhaseEngine processor; it serves as
	  a working memory for the PhaseEngine processor as well
	location definitions overlap due to various sources giving different
	  scratch RAM layouts
	the PhaseEngine processor uses "ARG_1" and "ARG_2" to pass parameters
	  to the drivers and BIOS during sequencer interrupts; "RETURN_1" is used
	  to return results from the drivers and BIOS to the PhaseEngine code
	the PhaseEngine processor uses SCB pointer register's (SCBPTR) values
	  to link SCB in the lists, with value FFh indicating the end of list
SeeAlso: #9047,#9048

Format of the SCB array:
Offset	Size	Description	(Table P1003)
 00h	BYTE	"SCB_CONTROL"
		bit 7: need WDTR message (NEEDWDTR) or
		       "MK_MESSAGE"
		bit 6: disconnect enable (DISCENB)
		bit 5: tagging enable (TAG_ENB)
		bit 4: need SDTR message (NEEDSDTR) or
		       "MUST_DMAUP_SCB"
		bit 3: "ABORT_SCB"
		bit 2: "DISCONNECTED"
		bits 1-0: command tag type (SCB_TAG_TYPE)
 01h	BYTE	target/channel/LUN (SCB_TCL)
		bits 7-4: target ID
		bit 3: channel (0=A, 1=B)
		bits 2-0: LUN
 02h	BYTE	target status (SCB_TARGET_STATUS)
		SCSI status byte
 03h	BYTE	scatter/gather count (SCB_SGCOUNT)
 04h	DWORD	scatter/gather pointer (SCB_SGPTR)
 08h	BYTE	residual scatter/gather count (SCB_RESID_SGCNT)
 09h  3 BYTEs	residual data count (SCB_RESID_DCNT)
 0Ch	DWORD	data pointer (SCB_DATAPTR)
 10h  3 BYTEs	data count (SCB_DATACNT)
 13h	BYTE	next linked SCB index (SCB_LINKED_NEXT)
 14h	DWORD	command pointer (SCB_CMDPTR)
 18h	BYTE	command length (SCB_CMDLEN)
 19h	BYTE	command tag (SCB_TAG)
 1Ah	BYTE	next SCB index (SCB_NEXT)
 1Bh	BYTE	previous SCB index (SCB_PREV)
 1Ch  2	WORDs	busy targets (SCB_BUSYTARGETS)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
SeeAlso: #P1004,#P1014

Format of the scatter/gather segment:
Offset	Size	Description	(Table P1004)
 00h	DWORD	physical address
 04h	DWORD	length
SeeAlso: #P1003,#P1014

Bitfields for AHA-284x serial EEPROM control register (SEECTL):
Bit(s)	Description	(Table P1005)
 7-3	reserved
 2	chip select (CS)
 1	clock (CK)
 0	data out (DO)
Notes:	93C46 serial EEPROM chips have 1024 bits organized into 64 16-bit
	  words and use 6 bits to address each word
	only the first 32 words of serial EEPROM are used by the Adaptec BIOS
	bits 2-0 are connected to the chip select, clock, and data out pins of
	  the serial EEPROM respectively
	bit 1 must be pulled high and then low for a minimum of 750 and 250 ns
	  to provide clocking for the EEPROM chip
	bit 1 going from low to high causes the EEPROM chip to sample the data
	  out pin and initiates the next bit to be sent through the data in pin
	bit 2 must be set for a minimum of 1 mcs with the bit 1 goig high and
	  then low for the EEPROM chip to be selected; then the instruction can
	  be sent to the EEPROM chip
	instruction can be terminated by taking the EEPROM chip select pin low,
	  with the bit 1 going high and low
SeeAlso: #P1006,#P1007,#P1008

Bitfields for AHA-284x "STATUS" register:
Bit(s)	Description	(Table P1006)
 7	EEPROM timer fired? (EEPROM_TF)
 6-5	"BIOS_SEL"
 4-1	"ADSEL"
 0	data in (DI)
Notes:	bit 0 is connected to the data in pin of the serial EEPROM; it can be
	  read after the clock pin goes from high to low
	bit 7 is cleared after a read from the serial EEPROM control register
	  (SEECTL) and goes high 800 ns later
SeeAlso: #P1005,#P1007,#P1008

(Table P1007)
Values for the 93C46 serial EEPROM instructions:
Opcode	   Function  Parameter	Description
0000xxxxb  EWDS	     -		disable all programming instructions
0001xxxxb  WRAL	     D15..D0	write to all registers
0010xxxxb  ERAL	     -		erase all registers
0011xxxxb  EWEN	     -		write enable
				must precede all programming modes
01AAAAAAb  WRITE     D15..D0	write register with address A5..A0
10AAAAAAb  READ	     -		read registers starting with address A5..A0
11AAAAAAb  ERASE     -		erase register with address A5..A0
Notes:	while the chip select pin remains high an instuction and the optional
	  parameter word can be clocked in MSB first, beginning with the start
	  bit of 1
	16-bit parameter and data words are transferred MSB first, beginning
	  with the start bit of 0
SeeAlso: #P1005,#P1006

Format of the AHA-284x serial EEPROM:
Address	Size	Description	(Table P1008)
 00h  16 WORDs	SCSI ID configuration (see #P1009)
 10h	WORD	BIOS control (see #P1011)
 11h	WORD	host adapter control (see #P1012)
 12h	WORD	bus release time / host adapter ID (see #P1013)
 13h	WORD	maximum targets (see #P1014)
 14h  11 WORDs	reserved
 1Fh	WORD	checksum
SeeAlso: #P1005,#P1006

Bitfields for the serial EEPROM SCSI ID configuration word:
Bit(s)	Description	(Table P1009)
 15-11	reserved
 10	report even if not found (CFRNFOUND)
 9	include in BIOS scan (CFINCBIOS)
 8	send START UNIT SCSI command (CFSTART)
 7-6	reserved
 5	(Wide SCSI) wide bus device (CFWIDEB)
 4	enable disconnection (CFDISC)
 3	enable synchronous transfer (CFSYNCH)
 2-0	synchronous transfer rate (CFXFER)
SeeAlso: #P0605,#P1008

Bitfields for the serial EEPROM BIOS control word:
Bit(s)	Description	(Table P1011)
 15-6	reserved
 5	extended translation (CFEXTEND)
 4	support more than 2 drives (CFSM2DRV)
 3	reserved
 2	BIOS enabled (CFBIOSEN)
 1	support removable drives for boot only (CFSUPREMB)
 0	support all removable drives (CFSUPREM)
SeeAlso: #P1008

Bitfields for the serial EEPROM host adapter control word:
Bit(s)	Description	(Table P1011)
 15-7	reserved
 6	reset SCSI bus at IC initialization (CFRESETB)
 5	SCSI low byte termination (CFSTERM)
	=0 disable
	=1 enable
 4	SCSI parity (CFSPARITY)
	=0 disable
	=1 enable
 3-2	FIFO threshold (CFFIFO)
 1-0	selection timeout (CFSELTO)
SeeAlso: #P0600,#P0980,#P0994,#P1008

Bitfields for the serial EEPROM bus release time / host adapter ID word:
Bit(s)	Description	(Table P1012)
 15-8	bus release time (CFBRTIME)
 7-4	reserved
 3-0	host adapter SCSI ID (CFSCSIID)
SeeAlso: #P0982,#P0989,#P1007

Bitfields for the serial EEPROM maximum targets word:
Bit(s)	Description	(Table P1013)
 15-8	reserved
 7-0	maximum targets (CFMAXTARG)
SeeAlso: #P1007

Bitfields for the PhaseEngine SCSI sequence processor instruction:
Bit(s)	Description	(Table P1014)
 31-29	reserved (0)
 28-25	opcode
	0000 OR	 dest,imm[,src] [RET]
	     MVI dest,imm [RET]
	0001 AND dest,imm[,src] [RET]
	     MOV dest,src [RET]
	     CLR dest [RET]
	     NOP [RET]
	     RET
	0010 XOR dest,imm[,src] [RET]
	     NOT dest [RET]
	0011 ADD dest,imm[,src] [RET]
	     INC dest[,src] [RET]
	     DEC dest[,src] [RET]
	     CLC [dest[,imm]] [RET]
	     STC dest [RET]
	0100 ADC dest,imm[,src] [RET]
	0101 SHL/SHR/ROL/ROR dest,[src,]imm [RET]
	1000 OR	 src,imm JMP addr
	     MOV src JMP addr
	     MVI imm JMP addr
	     JMP addr
	1001 OR	 src,imm JC addr
	     MOV src JC addr
	     MVI imm JC addr
	     JC addr
	1010 OR	 src,imm JNC addr
	     MOV src JNC addr
	     MVI imm JNC addr
	     JNC addr
	1011 OR	 src,imm CALL addr
	     MOV src CALL addr
	     MVI imm CALL addr
	     CALL addr
	1100 CMP  src,imm JNE addr
	1101 TEST src,imm JNZ addr
	1110 CMP  src,imm JE  addr
	1111 TEST src,imm JZ  addr
	others reserved
 24-16	(jump instructions) instruction address
 24	(non-jump instructions) return flag
 23-16	(non-jump instructions) destination register address
 15-8	source register address
 7-0	(shift instructions) shift control (see #P1015)
	(other instructions) immediate data
	if 0 accumulator register (ACCUM) is used instead
Notes:	the jump instructions with the OR/MOV/MVI prefixes implicitly use the
	  source index register (SINDEX) as destination
SeeAlso: #P0989,#P0990,#P0991,#P0995,#P0996,#P0997,#9042

Bitfields for the PhaseEngine shift control:
Bit(s)	Description	(Table P1015)
 7	clear all bits?
 6-4	number of bits to shift the AND mask (FFh)
 3	=0 shift the AND mask left
	=1 shift the AND mask right
 2-0	number of bits to rotate the source left
Notes:	the 8-bit source seems to be rotated left and then AND'ed with the mask
	  (FFh) which is shifted left or right prior to AND'ing in order to
	  perform all kinds of the shift/rotate instructions
	bit 7 is set (and bits 6-4 equal 7) if the shift count is greater than
	  7 specified for the SHL/SHR instructions
----------P1C65------------------------------
PORT 1C65 - Compaq Contura Aero
SeeAlso: PORT 2065h

1C65  R?  bit 6: operating on battery power
--------X-P1C801C8F--------------------------
PORT 1C80-1C8F - VESA XGA Video in EISA slot 1

1C80-1C83  RW	EISA Video ID
1C84  RW	EISA Video expansion board control (see #P1016)
1C85  RW	EISA Setup control
1C88  RW	EISA Video Programmable Option Select 0
1C89-1C8F  RW	EISA Video Programmable Option Select 1-7
--------X-P1C801C83--------------------------
PORT 1C80-1C83 - EISA board product ID (board in slot 1)

1C80  R?  bit 7: unused (0)
	  bits 6-2: manufacturer ID, first compressed ASCII char
	  bits 1-0: manufacturer ID, second compressed ASCII char (high)
1C81  R?  bits 7-5: manufacturer ID, second compressed ASCII char (low)
	  bits 4-0: manufacturer ID, third compressed ASCII char
1C82  R?  bits 7-4: first hex digit of product type
	  bits 3-0: second hex digit of product type
1C83  R?  bits 7-4: third hex digit of product type
	  bits 3-0: product revision number (hex digit)
--------X-P1C84------------------------------
PORT 1C84 - EISA CONFIGURATION FLAGS (board in slot 1)

1C84  RW  configuration flags (see #P1016)

Bitfields for EISA Add-in Card configuration flags:
Bit(s)	Description	(Table P1016)
 0	enable
 1	IOCHKERR (read-only) card is generating CHCHK#, causing an NMI
 2	IOCHKRST reset card
 7-3	card-specific
--------X-P1C85------------------------------
PORT 1C85 - EISA SETUP CONTROL (board in slot 1)
--------V-P1C85------------------------------
PORT 1C85 - Compaq Qvision EISA - Virtual Controller ID
--------X-P1C881C8F--------------------------
PORT 1C88-1C8F - EISA PROGRAMMABLE OPTION SELECT (board in slot 1)
--------V-P1EE81EEF--------------------------
PORT 1EE8-1EEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VSYNC WIDTH

1EE8w -W  CRT control: vertical sync width
--------V-P1EEC------------------------------
PORT 1EEC - Mach64 - ???

1EEC  RW  display power and other controls
	bits 3-2: DPMS power mode
		00 normal
		01 standby
		10 suspend
		11 off
--------X-P200020FF--------------------------
PORT 2000-20FF - available for EISA slot 2
----------P2065------------------------------
PORT 2065 - Compaq Contura Aero
SeeAlso: PORT 1C65h"Compaq",PORT 2465h"Compaq"

2065  -W  ??? (84h seen)
--------V-P2100------------------------------
PORT 2100 - XGA Video Operating Mode Register
Note:	this port is for the first XGA in the system; 2110-2170 are used for
	  the second through eighth XGAs
--------V-P2101------------------------------
PORT 2101 - XGA Video Aperture Control
Note:	this port is for the first XGA in the system; 2111-2171 are used for
	  the second through eighth XGAs
--------V-P21022103--------------------------
PORT 2102-2103 - XGA ???
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2104------------------------------
PORT 2104 - XGA Video Interrupt Enable
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2105------------------------------
PORT 2105 - XGA Video Interrupt Status
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2106------------------------------
PORT 2106 - XGA Video Virtual Memory Control
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2107------------------------------
PORT 2107 - XGA Video Virtual Memory Interrupt Status
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2108------------------------------
PORT 2108 - XGA Video Aperture Index
Note:	this port is for the first XGA in the system; 211x-217x are used for
	  the second through eighth XGAs
--------V-P2109------------------------------
PORT 2109 - XGA Video Memory Access Mode
Note:	this port is for the first XGA in the