ports.c

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Bit(s)	Description	(Table P0981)
 7	(Wide SCSI) wide transfer control (WIDEXFER)
 6-4	synchronous transfer rate (SXFR)
 3-0	synchronous offset (SOFS)
SeeAlso: #P0605,#P0984

Bitfields for SCSI ID register (SCSIID):
Bit(s)	Description	(Table P0982)
 7-4	target ID (TID)
 3-0	our ID (OID)
SeeAlso: #P0606,#P0987,#P1012

Bitfields for clear SCSI interrupt register 0 (CLRSINT0):
Bit(s)	Description	(Table P0983)
 7	reserved?
 6	clear selection out done (CLRSELDO)
 5	clear selection in  done (CLRSELDI)
 4	clear selection in progress (CLRSELINGO)
 3	clear SCSI counter wrap (CLRSWRAP)
 2	reserved
 1	clear SCSI PIO ready (CLRSPIORDY)
 0	reserved
SeeAlso: #P0600,#P0601,#P0607,#P0608,#P0616

Bitfields for SCSI status register 2 (SSTAT2):
Bit(s)	Description	(Table P0984)
 7	"OVERRUN"
 6-5	reserved
 4-0	SCSI FIFO count? (SFCNT)
SeeAlso: #P0979,#P0981

Bitfields for SCSI test control register (SCSITEST):
Bit(s)	Description	(Table P0985)
 7-3	reserved
 2	"RQAKCNT"
 1	"CNTRTEST"
 0	"CMODE"
SeeAlso: #P0988

Bitfields for selection timeout timer register (SELTIMER):
Bit(s)	Description	(Table P0986)
 7-6	reserved
 5	"STAGE6"
 4	"STAGE5"
 3	"STAGE4"
 2	"STAGE3"
 1	"STAGE2"
 0	"STAGE1"
SeeAlso: #P0980

Bitfields for selection/reselection ID register (SELID):
Bit(s)	Description	(Table P0987)
 7-4	selecting device ID (SELID)
 3	one bit (ONEBIT)
 2-0	reserved
Note:	bit 3 is set when the selecting/reselecting device did not set its own
	  ID on the SCSI bus
SeeAlso: #P0600,#P0607,#P0982


Bitfields for SCSI block control register (SBLKCTL):
Bit(s)	Description	(Table P0988)
 7-6	reserved
 5	auto-flush disable (AUTOFLUSHDIS)
 4	reserved
 3	select bus (SELBUS)
	=0 select bus A
	=1 select bus B (SELBUSB)
 2	reserved
 1	"SELWIDE"
 0	reserved
Notes:	bit 1 allows for the coexistence of 8-bit and 16-bit devices on a Wide
	  SCSI bus
	in a twin channel configuration addresses 00h-1Eh are gated to the
	  appropriate channel based on the value of bit 3
	bit 5 is read only on the AIC-7770 revisions prior to E

Bitfields for sequencer control register (SEQCTL):
Bit(s)	Description	(Table P0989)
 7	parity error disable (PERRORDIS)
 6	pause disable (PAUSEDIS)
 5	"FAILDIS"
 4	fast mode (FASTMODE)
 3	break address interrupt enable (BRKADRINTEN)
 2	"STEP"
 1	sequencer reset (SEQRESET)
 0	load sequencer RAM (LOADRAM)
Notes:	setting bit 1 causes the sequencer to be paused; the sequencer address
	  register is reset to 0
	bit 7 should be reset while loading the sequencer RAM; after loading
	  is complete, bit 0 should be cleared before changing the sequencer
	  address register (SEQADDR) to avoid sequencer RAM parity errors
SeeAlso: #P0990,#P0996,#P0997,#P0998,#P1014

Bitfields for sequencer address register (SEQADDR):
Bit(s)	Description	(Table P0990)
 15-9	reserved
 8-0	sequencer RAM address
Notes:	bits 8-0 contain the address of a DWORD in the sequencer RAM; it points
	  to the next instruction to be execute or load into RAM
	setting bit 1 in the sequencer control register (SEQCTL) resets this
	  address to 0
	when the PhaseEngine processor is paused, the sequencer address can be
	  altered and a sequencer program can be loaded by writing it, byte by
	  byte, to the sequencer RAM data register (SEQRAM); the address is
	  auto-incremented after the high BYTE of each DWORD is loaded
SeeAlso: #P0989,#P1014

Bitfields for flags register (FLAGS):
Bit(s)	Description	(Table P0991)
 7-2	reserved
 1	zero  flag (ZERO)
 0	carry flag (CARRY)
SeeAlso: #P1014

Bitfields for board control register (BCTL):
Bit(s)	Description	(Table P0992)
 7-4	reserved
 3	"ACE"
 2-1	reserved
 0	enable board (ENABLE)
Note:	bit 3 is somehow related to the support for the external processors

Bitfields for bus on/off time register (BUSTIME):
Bit(s)	Description	(Table P0993)
 7-4	bus off time (BOFF)
	in 4 BCLK cycle units?
 3-0	bus on	time (BON)
SeeAlso: #P0994,#P1002

Bitfields for bus speed register (BUSSPD):
Bit(s)	Description	(Table P0994)
 7-6	DMA FIFO threshold (DFTHRSH)
	11 100?
 5-3	"STBOFF"
 2-0	"STBON"
SeeAlso: #P0993,#P0999,#P1000,#P1002

Bitfields for host control register (HCNTRL):
Bit(s)	Description	(Table P0995)
 7	reserved
 6	power down (POWRDN)
 5	reserved
 4	software interrupt (SWINT)
 3	IRQ mode select (IRQMS)
	=0 level-sensitive
	=1 edge-triggered
 2	pause sequencer (PAUSE)
 1	interrupt enable (INTEN)
 0	chip reset (CHIPRST)
Notes:	bit 0 is self-clearing (though on some AIC-7771 based boards it stucks
	  set, and must be manually cleared)
	set bit 2 to pause the sequencer, then poll the register until this bit
	  reads as 1 indicating that the sequencer has actually stopped; the
	  sequencer can disable pausing for critical sections through bit 6 of
	  the sequencer control register (SEQCTL)
SeeAlso: #P0989,#P1014

Bitfields for interrupt status register (INTSTAT):
Bit(s)	Description	(Table P0996)
 7-4	sequencer status
	0000 unknown SCSI bus phase (BAD_PHASE)
	0001 sending MESSAGE REJECT (SEND_REJECT)
	0010 no IDENTIFY after reconnect (NO_IDENT)
	0011 no command match for reconnect (NO_MATCH)
	0100 SYNCRONOUS DATA TRANSFER REQUEST (SDTR) message received (SDTR_MSG)
	0101 WIDE DATA TRANSFER REQUEST (WDTR) message received (WDTR_MSG)
	0110 MESSAGE REJECT received (REJECT_MSG)
	0111 bad status from target (BAD_STATUS)
	1000 residual byte count non-zero (RESIDUAL)
	1001 sent ABORT TAG message (ABORT_TAG)
	1010 awaiting message
	1011 immediate command completed (IMMEDDONE)
	1100 message buffer busy (MSG_BUFFER_BUSY)
	1101 MESSAGE IN phase mismatch (MSGIN_PHASEMIS)
	1110 data overrun (DATA_OVERRUN)
 3	break address interrupt (BRKADRINT)
 2	SCSI interrupt (SCSIINT)
 1	command complete interrupt (CMDCMPLT)
 0	sequencer interrupt (SEQINT)
Notes:	the PhaseEngine processor can set bit 0 to interrupt the CPU requesting
	  some service from it; an interrupt reason is passed in bits 7-4
	the PhaseEngine processor sets bit 1 after placing a completed SCB into
	  the queue out FIFO
	setting bit 0 pauses the PhaseEngine processor; it needs unpausing via
	  resetting bit 2 of the host control register (HCNTRL)
SeeAlso: #P0986,#P0993,#P0995,#P1014

Bitfields for hard error register (ERROR):
Bit(s)	Description	(Table P0997)
 7-4	reserved
 3	sequencer RAM parity error (PARERR)
 2	illegal opcode in sequencer program (ILLOPCODE)
 1	illegal sequencer address referenced (ILLSADDR)
 0	illegal host access (ILLHADDR)
Note:	usually a full board reset is required after detecting a hard error
SeeAlso: #P1014

Bitfields for clear interrupt status register (CLRINT):
Bit(s)	Description	(Table P0998)
 7-4	reserved
 3	clear break address interrupt (CLRBRKADRINT)
 2	clear SCSI interrupt (CLRSCSIINT)
 1	clear command complete interrupt (CLRCMDINT)
 0	clear sequencer interrupt (CLRSEQINT)
SeeAlso: #P0986,#P0991,#P1014

Bitfields for DMA FIFO control register (DFCNTRL):
Bit(s)	Description	(Table P0999)
 7	reserved
 6	"WIDEODD"
 5	SCSI enable (SCSIEN)
 4	SCSI DMA enable? (SDMAEN)
 3	host DMA enable? (HDMAEN)
 2	"DIRECTION"
	=0 SCSI to host
	=1 host to SCSI
 1	FIFO flush (FIFOFLUSH)
 0	FIFO reset (FIFORESET)
Notes:	this register allows the PhaseEngine processor to control DMA transfers
	  from/to host memory
	bits 3 and 4 clear automatically when host and SCSI DMA is complete
	  respectively
SeeAlso: #P0994,#P1000

Bitfields for DMA FIFO status register (DFSTATUS):
Bit(s)	Description	(Table P1000)
 7-6	reserved
 5	"DWORDEMP"
 4	"MREQPEND"
 3	host DMA done (HDONE)
 2	DMA FIFO threshold? (DFTHRESH)
 1	FIFO full  (FIFOFULL)
 0	FIFO empty (FIFOEMP)
SeeAlso: #P0994,#P0999

Bitfields for SCB auto-increment register (SCBCNT):
Bit(s)	Description	(Table P1001)
 7	SCB auto-increment (SCBAUTO)
 6-5	reserved
 4-0	SCB counter (SCBCNT)
Note:	this register allows CPU to quickly upload/download the SCBs to/from
	  the SCB RAM; if bit 7 is set any reference to addresses A0h-BFh post-
	  increments bits 4-0 of this register containing the offset into the
	  SCB array which is to be accessed next; on the AHA-284x only 8-bit
	  transfers can be used
SeeAlso: #P1003

Format of the scratch RAM:
Offset	Size	Description	(Table P1002)
 00h 16 BYTEs	target scratch (TARG_SCRATCH) (see #9025)
 10h	WORD	channel A Ultra SCSI enable (ULTRA_ENB_A)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 10h	BYTE	rejected byte (REJBYTE)
 11h	BYTE	channel B Ultra SCSI enable (ULTRA_ENB_B)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 11h	BYTE	rejected byte extended (REJBYTE_EXT)
 11h	BYTE	rejected byte (REJBYTE)
 12h	BYTE	channel A disable disconnect (DISC_DSB_A)
 13h	BYTE	channel B disable disconnect (DISC_DSB_B)
 14h	BYTE	length of pending message (MSG_LEN)
 15h  8 BYTEs	outgoing message (MSG0-MSG7)
 15h	BYTE	pending	 message flag (MSG_FLAGS)
 16h	BYTE	length of pending message (MSG_LEN)
 17h  ? BYTEs	outgoing message body (MSG_START)
 1Dh	BYTE	parameters for DMA logic (DMAPARAMS) (see #P0999)
 1Dh	BYTE	last phase (LASTPHASE)
 1Eh	BYTE	"SEQ_FLAGS"
		bit 7: "RESELECTED"
		bit 6: "IDENTIFY_SEEN"
		bit 5: "TAGGED_SCB"
		bit 4: data phase seen (DPHASE)
		bit 3: reserved
		bit 2: page SCBs (PAGESCBS)
		bit 1: "WIDE_BUS"
		bit 0: "TWIN_BUS"
 1Eh	BYTE	"ARG_1"
		bit 0: "MAXOFFSET"
 1Fh	BYTE	saved target/channel/LUN (SAVED_TCL)
		bits 7-4: target ID
		bit 3: channel (0=A, 1=B)
		bits 2-0: LUN
 1Fh	BYTE	"RETURN_1"
		00h do nothing
		10h SCB paged in (SCB_PAGEDIN)
		20h send MESSAGE REJECT message (SEND_REJ)
		40h send REQUEST SENSE	command (SEND_SENSE)
		60h send SYNCHRONOUS DATA TRANSFER REQUEST message (SEND_SDTR)
		80h send WIDE DATA TRANSFER REQUEST message (SEND_WDTR)
 20h	BYTE	scatter/gather count (SG_COUNT)
 20h	BYTE	"SIGSTATE"
 21h	DWORD	scatter/gather next segment pointer (SG_NEXT)
 21h	BYTE	parameters for DMA logic (DMAPARAMS) (see #P0999)
 22h	BYTE	scatter/gather count (SG_COUNT)
 23h	DWORD	scatter/gather next segment pointer (SG_NEXT)
 25h	BYTE	waiting SCB list head (WAITING_SCBH)
 26h	BYTE	saved link pointer (SAVED_LINKPTR)
 27h	BYTE	saved SCB pointer (SAVED_SCBPTR)
 27h	BYTE	SCB count (SCBCOUNT)
		number of SCBs supported in hardware
 28h	BYTE	last phase (LASTPHASE) (see #9003)
		bit 7: -C/D input (CDI)
		bit 6: -I/O input (IOI)
		bit 5: -MSG input (MSGI)
		bits 4-0: reserved
 28h	BYTE	negative SCB count (COMP_SCBCOUNT)
 29h	BYTE	extended message length (MSGIN_EXT_LEN)
 29h	BYTE	queue count mask (QCNTMASK)
		works around a bug in AIC-7850
 2Ah	BYTE	extended message opcode (MSGIN_EXT_OPCODE)
 2Ah	BYTE	"FLAGS"
		bit 7: "RESELECTED"
		bit 6: IDENTIFY message seen (IDENTIFY_SEEN)
		bit 5: "SELECTED"
		bit 4: data phase seen (DPHASE)
		bit 3: reserved
		bit 2: page SCBs (PAGESCBS)
		bit 1: wide bus	 (WIDE_BUS)
		bit 0: twin bus	 (TWIN_BUS)
 2Bh  3	BYTEs	extended message tail bytes (MSGIN_EXT_BYTES)
 2Bh	BYTE	saved target/channel/LUN (SAVED_TCL)
		bits 7-4: target ID
		bit 3: channel (0=A, 1=B)
		bits 2-0: LUN
 2Ch	WORD	channel A active targets (ACTIVE_A)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
 2Ch	BYTE	"ARG_1" or "RETURN_1"
 2Dh	BYTE	channel B active targets (ACTIVE_B)
		bit N is set if there's untagged SCSI command currently active
		  on the target ID N
 2Dh	BYTE	"ARG_2"
 2Eh	BYTE	disconnected SCB list head (DISCONNECTED_SCBH)
 2Eh	BYTE	waiting SCB list head (WAITING_SCBH)
 2Eh	BYTE	signal state (SIGSTATE)
 2Fh	BYTE	free SCB list head (FREE_SCBH)
		disconnected SCB list head (DISCONNECTED_SCBH)
 2Fh	BYTE	"NEEDSDTR"
		bit N if set means that the synchronous data transfer needs to
		  be negotiated with the target ID N
 30h	DWORD	"HSCB_ADDR"
 30h	BYTE	saved link pointer (SAVED_LINKPTR)
 31h	BYTE	saved SCB  pointer (SAVED_SCBPTR)
 32h	WORD	channel A Ultra enable (ULTRA_ENB)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 33h	BYTE	channel B Ultra enable (ULTRA_ENB_B)
		bit N if set means Ultra SCSI transfers are enabled for the
		  target ID N
 34h	BYTE	"CUR_SCBID"
 35h	BYTE	"CMDOUTCNT"
		count of commands placed in the out FIFO
 36h	BYTE	SCB count (SCBCOUNT)
		number of SCBs supported in hardware
 36h	BYTE	"ARG_1" or "RETURN_1"
		bit 7: "SEND_MSG"