ports.c

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+00F  RW  local memory/32-bit I/O (byte 3) IO port high
--- I/O bank 1 ---
+001  RW  bank 1 register 1 (see #P0969)
+002  RW  int select register (see #P0970)
+003  RW  I/O mapping register (see #P0971)
+004  RW  reserved
+005  RW  reserved
+006  RW  reserved
+007  RW  RCV BOF treshold reg
+008  RW  RCV lower limit reg high byte
+009  RW  RCV upper limit reg high byte
+00A  RW  XMT lower limit reg high byte
+00B  RW  XMT upper limit reg high byte
+00C  RW  FLASH control register (see #P0972)
+00D  RW  bank 1 register 13 (see #P0973)
+00E  RW  reserved
+00F  RW  reserved
--- I/O bank 2 ---
+001  RW  bank 2 register 1 (see #P0974)
+002  RW  bank 2 register 2 (see #P0975)
+003  RW  bank 2 register 3 (see #P0976)
+004  RW  individual address register 0
+005  RW  individual address register 1
+006  RW  individual address register 2
+007  RW  individual address register 3
+008  RW  individual address register 4
+009  RW  individual address register 5
+00A  RW  bank 2 register 10 (see #P0977)
+00B  RW  RCV NO resource counter
+00C  RW  IAPROM IO port
+00D  RW  reserved
+00E  RW  reserved
+00F  RW  reserved
------

Bitfields for Intel 82595TX command register:
Bit(s)	Description	(Table P0965)
 7-6	bank pointer (if switch bank command written; ignored for other
	  commands)
	00 = bank 0
	01 = bank 1
	10 = bank 2
 5	command (other than transmit) aborted (read-only; should be written 0)
 4-0	(write) command OP code
	00h = switch bank/nop
	03h = MC-setup
	04h = transmit
	05h = TDR
	06h = dump
	07h = diagnose
	08h = RCV enable
	0Ah = RCV disable
	0Bh = RCV stop
	0Dh = abort
	0Eh = reset
	14h = XMT no CRC/SA
	15h = cont XMT test
	16h = set tristate
	17h = reset tristate
	18h = power down
	1Ch = resume XMT list
	1Eh = sel reset
	(read) execution event (MC done, init done, TDR done, DIAG done)
	  (if bank 0 register 1 bit 3 = 1)
SeeAlso: #P0966,#P0968

Bitfields for Intel 82595TX status register:
Bit(s)	Description	(Table P0966)
 7-6	RCV states
 5-4	EXEC states
 3	EXEC INT
 2	TX INT
 1	RX INT
 0	RX STP INT
SeeAlso: #P0965,#P0967,#P0968

Bitfields for Intel 82595TX id register:
Bit(s)	Description	(Table P0967)
 7-6	counter
 5	reserved (1)
 4	auto enable
 3-2	reserved (01)
 1-0	reserved (0)
SeeAlso: #P0965,#P0966,#P0968

Bitfields for Intel 82595TX mask register:
Bit(s)	Description	(Table P0968)
 7-6	reserved
 5	cur/base
 4	32IO/HAR
 3	EXEC mask
 2	TX mask
 1	RX mask
 0	RX STP mask
SeeAlso: #P0965,#P0966,#P0969

Bitfields for Intel 82595TX bank 1 register 1:
Bit(s)	Description	(Table P0969)
 7	tri-st INT
 6	alt RDY tm
 5-2	reserved
 1	host bus wd
 0	reserved
SeeAlso: #P0965,#P0967,#P0970

Bitfields for Intel 82595TX int select register:
Bit(s)	Description	(Table P0970)
 7	FL/BT detect
 6-4	boot EPROM/FLASH decode window
 3	reserved
 2-0	INT select

Bitfields for Intel 82595TX I/O mapping register:
Bit(s)	Description	(Table P0971)
 7-6	reserved
 5-0	I/O mapping window

Bitfields for Intel 82595TX FLASH control register:
Bit(s)	Description	(Table P0972)
 7-6	FLASH page select high
 5-4	FLASH write enable
 3-0	FLASH page select

Bitfields for Intel 82595TX bank 1 register 13:
Bit(s)	Description	(Table P0973)
 7-3	reserved
 2	SMOUT out en
 1	AL RDY test
 0	AL RDY PAS/FL

Bitfields for Intel 82595TX bank 2 register 1:
Bit(s)	Description	(Table P0974)
 7	disc bad fr
 6	TX chn ErStp
 5	TX chn int md
 4	PCMCIA/ISA
 3-1	reserved
 0	TX con proc en

Bitfields for Intel 82595TX bank 2 register 2:
Bit(s)	Description	(Table P0975)
 7-6	loopback
 5	multi IA
 4	no SA ins
 3	length enable
 2	RX CRC InMem
 1	BC DIS
 0	PRMSC mode

Bitfields for Intel 82595TX bank 2 register 3:
Bit(s)	Description	(Table P0976)
 7	test 1
 6	test 2
 5	BNC/TPE
 4	APORT
 3	jabber disable
 2	TPE/AUI
 1	pol/corr
 0	lnk in disable

Bitfields for Intel 82595TX bank 2 register 10:
Bit(s)	Description	(Table P0977)
 7-5	stepping
 4	trnoff enable
 3	EEDO
 2	EEDI
 1	EECS
 0	EESK
--------X-P100010FF--------------------------
PORT 1000-10FF - available for EISA slot 1
----------P12E812EF--------------------------
PORT 12E8-12EF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VERT TOTAL

12E8w -W  CRT control: vertical total
--------V-P12EE------------------------------
PORT 12EE - ATI Mach32 - CONFIGURATION STATUS 0
SeeAlso: PORT 16EEh"Mach32",PORT 42EEh"Mach32",PORT 52EEh"Mach32"
----------P13901393--------------------------
PORT 1390-1393 - cluster (adapter 3)
----------P13C6------------------------------
PORT 13C6 - Compaq - ???
Note:	this port is read by the Compaq MS-DOS 4.0/5.0 CHARSET utility

13C6  R?  Compaq video status??? (see #P0978)

Bitfields for Compaq video status???:
Bit(s)	Description	(Table P0978)
 7	???
 6	flag
 5-3	???
 2-0	status of display???
--------X-P140014FF--------------------------
PORT 1400-14FF - available for EISA slot 1
----------P16E816EF--------------------------
PORT 16E8-16EF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VERT DISPLYD

16E8w -W  CRT control: vertical displayed
--------V-P16EE------------------------------
PORT 16EE - ATI Mach32 - CONFIGURATION STATUS 1
SeeAlso: PORT 12EEh"Mach32",PORT 42EEh"Mach32",PORT 52EEh"Mach32"
--------X-P180018FF--------------------------
PORT 1800-18FF - available for EISA slot 1
----------P1AE81AEF--------------------------
PORT 1AE8-1AEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - VSYNC START

1AE8w -W  CRT control: vertical sync start
--------X-P1C001CFF--------------------------
PORT 1C00-1CFF - available for EISA slot 1
--------d-P1C001CBF--------------------------
PORT 1C00-1CBF -  Adaptec AIC-777x EISA SCSI controller in EISA slot 1
Notes:	Adaptec AIC-777x SCSI controllers have on-board PhaseEngine SCSI
	  sequence processor which executes its instructions from the 2-Kbyte
	  sequencer RAM; it treats all of the CPU-addressable registers as its
	  data memory
	AIC-777x SCSI controllers have special on-board RAM and queue registers
	  for queueing the requests sent from the drivers and BIOS to the
	  PhaseEngine processor
	Adaptec AHA-284x is a VLB SCSI controller based on AIC-7770; it has
	  a serial EEPROM (93C46) for storing various configuration settings
SeeAlso: PORT 0340h-035Fh"Adaptec AHA-152x",PORT xxxxh"Adaptec AIC-78xx"

+000  RW  SCSI sequence control register (SCSISEQ) (see #P0600)
+001  RW  SCSI transfer control register 0 (SXFRCTL0) (see #P0979)
+002  RW  SCSI transfer control register 1 (SXFRCTL1) (see #P0980)
+003  R-  SCSI control signal read  register (SCSISIGI) (see #P0603)
+003  -W  SCSI control signal write register (SCSISIGO) (see #P0604)
+004  RW  SCSI rate control register (SCSIRATE) (see #P0981)
+005  RW  SCSI ID register (SCSIID) (see #P0982)
+006  RW  SCSI latched data low register (SCSIDATL)
	  read/write causes -ACK to pulse
+007  RW  (Wide SCSI) SCSI latched data high register (SCSIDATH)
	  read/write causes -ACK to pulse
+008  RW  SCSI transfer count register (STCNT) (3 bytes long)
+00B  R-  SCSI status register 0 (SSTAT0) (see #P0607)
+00B  -W  clear SCSI interrupt register 0 (CLRSINT0) (see #P0983)
+00C  R-  SCSI status register 1 (SSTAT1) (see #P0609)
+00C  -W  clear SCSI interrupt register 1 (CLRSINT1) (see #P0610)
+00D  R-  SCSI status register 2 (SSTAT2) (see #P0984)
+00E  R-  SCSI status register 3 (SSTAT3) (see #P0612)
+00F  RW  SCSI test control register (SCSITEST) (see #P0985)
+010  RW  SCSI interrupt mode register 0 (SIMODE0) (see #P0616)
+011  RW  SCSI interrupt mode register 1 (SIMODE1) (see #P0617)
+012  RW  SCSI data bus low register (SCSIBUSL)
+013  RW  (Wide SCSI) SCSI data bus high register (SCSIBUSH)
+014d R-  SCSI/host address register (SHADDR)
+018  RW  selection timeout timer  register (SELTIMER) (see #P0986)
+019  RW  selection/reselection ID register (SELID) (see #P0987)
+01F  RW  SCSI block control register (SBLKCTL) (see #P0988)
+020  RW  scratch RAM (64 bytes) (see #P1002)
+060  RW  sequencer control  register (SEQCTL)	(see #P0989)
+061  RW  sequencer RAM data register (SEQRAM)
+062w RW  sequencer address  register (SEQADDR) (see #P0990)
+064  RW  accumulator  register (ACCUM)
+065  RW  source index register (SINDEX)
+066  RW  destination index register (DINDEX)
+069  R-  all ones register (ALLONES)
	  always reads as FFh
+06A  R-  all zeros register (ALLZEROS)
	  always reads as 00h
+06B  R-  flags register (FLAGS) (see #P0991)
	  PhaseEngine processor's flags
+06C  R-  source indirect register (SINDIR)
+06D  -W  destination indirect register (DINDIR)
+06E  RW  function 1 register (FUNCTION1)
+06F  R-  "STACK"
+084  RW  board control register (BCTL) (see #P0992)
+085  RW  bus on/off time register (BUSTIME) (see #P0993)
+086  RW  bus speed register (BUSSPD) (see #P0994)
+087  RW  host control register (HCNTRL) (see #P0995)
+088d RW  host address register (HADDR)
+08C  RW  host counter register (HCNT) (3 bytes long)
+090  RW  sequence control block (SCB) pointer register (SCBPTR)
+091  RW  interrupt status register (INTSTAT) (see #P0996)
+092  R-  hard error register (ERROR) (see #P0997)
+092  -W  clear interrupt status register (CLRINT) (see #P0998)
+093  RW  DMA FIFO control register (DFCNTRL)  (see #P0999)
+094  R-  DMA FIFO status  register (DFSTATUS) (see #P1000)
+099  RW  DMA FIFO data register (DFDAT)
+09A  RW  SCB auto-increment register (SCBCNT) (see #P1001)
+09B  RW  queue in FIFO register (QINFIFO)
	  write places the value into the FIFO, read removes
+09C  R-  queue in count register (QINCNT)
	  number of the SCBs in the queue in
+09D  R-  queue out FIFO register (QOUTFIFO)
	  read removes the value from the FIFO
+09E  R-  queue out count register (QOUTCNT)
	  number of the SCBs in the queue out
+0A0  RW  SCB array (32 bytes) (see #P1003)
+0C0  RW  (AHA-284x) serial EEPROM control register (SEECTL) (see #P1005)
+0C1  RW  (AHA-284x) "STATUS" (see #P1006)
Notes:	the SCSI latched data registers are used to transfer data on the SCSI
	  bus during automatic or manual PIO mode
	in a twin channel configuration the separate register set with the
	  addresses 00h-1Eh exists for each channel
	the SCSI/host address register (SHADDR) holds the host address for the
	  byte about to be transfered on the SCSI bus; it is counted up in the
	  same manner as SCSI transfer count register (STCNT) is counted down
	  and should always be used to determine the address of the last byte
	  transfered since the host address register (HADDR) can be skewed by
	  read ahead
	the source/destination index registers (SINDEX/DINDEX) are used by the
	  PhaseEngine processor to indirectly address the data memory (i.e. the
	  CPU-addressable registers); the data byte addressed can be accessed
	  through the source/destination indirect registers (SINDIR/DINDIR)
	  respectively; the source index register (SINDEX) is auto-incremented
	  on each read from the source indirect register (SINDIR), while the
	  destination index register (DINDEX) is auto-incremented on each write
	  to the destination indirect register (DINDIR)
	the function 1 register (FUNCTION1) is used to convert the SCSI target
	  number to the corresponding bit mask; first, bits 6-4 are written
	  with a number N (other bits seems to be "don't care"), then the
	  register is read back, giving the bit mask having bit N set and all
	  other bits cleared
	the host address register (HADDR) and the host counter register (HCNT)
	  are used for the DMA transfers from/to the host memory
	the SCB pointer register (SCBPTR) selects the 32-byte area of the SCB
	  RAM to be mapped at addresses A0h-BFh
	the queue in/out FIFO registers (QINFIO/QOUTFIFO) hold the queue of
	  the SCB pointer register's (SCBPTR) values for addressing the SCBs
	  sent by CPU to the PhaseEngine processor and returned to CPU (when
	  the associated SCSI command completes) respectively; CPU selects
	  the SCB RAM area via the SCB pointer register (SCBPTR), downloads
	  prepared SCB to addresses A0h-BFh (this requeires the PhaseEngine
	  processor to be paused), then places the SCB pointer value to the
	  queue in FIFO by writing it to the respective register, from which
	  the SCB pointers can be read (and removed) in the FIFO order; the
	  PhaseEngine processor places the SCB pointer of the completed CCB
	  to the queue out FIFO by writing the respective register, and CPU
	  can remove it from the FIFO by reading the register

Bitfields for SCSI transfer control register 0 (SXFRCTL0):
Bit(s)	Description	(Table P0979)
 7	DMA FIFO on? (DFON)
 6	"DFPEXP"
 5	(Ultra SCSI) Ultra SCSI enable (ULTRAEN)
 4	clear SCSI transfer counter (CLRSTCNT)
 3	SCSI PIO enable (SPIOEN)
 2	SCAM enable (SCAMEN)
 1	clear channel (CLRCHN)
 0	reserved
SeeAlso: #P0607,#P0618,#P0620,#P0980,#P0984

Bitfields for SCSI transfer control register 1 (SXFRCTL1):
Bit(s)	Description	(Table P0980)
 7	bit bucket (BITBUCKET)
 6	SCSI counter wrap enable (SWRAPEN)
 5	enable SCSI parity check (ENSPCHK)
 4-3	selection time-out select (STIMESEL)
	00 256 ms
	01 128 ms
	10 64  ms
	11 32  ms
 2	enable selection timer (ENSTIMER)
 1	active negation enable (ACTNEGEN)
 0	SCSI terminator power enable? (STPWEN)
SeeAlso: #P0600,#P0979,#P0986

Bitfields for SCSI rate control register (SCSIRATE):