ports.c

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	  bits 4-0: manufacturer ID, third compressed ASCII char
0C82  R-  reserved for manufacturer's use
0C83  R-  bits 7-3: reserved for manufacturer's use
	  bits 2-0: EISA bus version
--------X-P0CF80CFF--------------------------
PORT 0CF8-0CFF - PCI Configuration Mechanism 1 - Configuration Registers
SeeAlso: PORT 0CF8h"Mechanism 2"

0CF8d -W  configuration address port (see #P0944)
0CFCd RW  configuration data port (when PORT 0CF8h bit 31 is set)

Bitfields for PCI configuration address port:
Bit(s)	Description	(Table P0944)
 1-0	reserved (00)
 7-2	configuration register number (see #00878)
 10-8	function
 15-11	device number
 23-16	bus number
 30-24	reserved (0)
 31	enable configuration space mapping
Note:	configuration registers are considered DWORDs, so the number in bits
	  7-2 is the configuration space address shifted right two bits
SeeAlso: #P0945
--------X-P0CF80CFA--------------------------
PORT 0CF8-0CFA - PCI Configuration Mechanism 2 - Configuration Registers
Notes:	this configuration mechanism is deprecated as of PCI version 2.1;
	  only mechanism 1 should be used for new systems
	to access the configuration space, write the target bus number to
	  the Forward Register, then write to the Configuration Space
	  Enable register, and finally read or write the appropriate I/O
	  port(s) in the range C000h to CFFFh (where Cxrrh accesses location
	  'rr' in physical device 'x's configuration data)
	the Intel "Saturn" and "Neptune" chipsets use configuration mechanism 2
SeeAlso: PORT 0CF8h"Mechanism 1",PORT C000h"PCI Configuration",PORT 0CFBh

0CF8  RW  Configuration Space Enable (CSE) (see #P0945)
0CFA  RW  Forward Register (selects target bus number)

Bitfields for PCI Configuration Space Enable:
Bit(s)	Description	(Table P0945)
 0	Special Cycle Enable (SCE)
 3-1	target function number (PCI logical device within physical device)
 7-4	key (non-zero to allow configuration)
SeeAlso: #P0944
----------P0CF9------------------------------
PORT 0CF9 - Intel chipsets - TURBO/RESET CONTROL REGISTER
Notes:	this port can only be accessed via 8-bit IN or OUT instructions by
	  the CPU
	supported by the Intel "Saturn" and "Neptune" (82434NX) chipsets,
	  the Intel 82454KX/GX (450GX chipset), Intel 82420EX chipset, etc.
SeeAlso: PORT C051h,#01055,#01239

0CF9  RW  reboot system, optionally selecting de-turbo mode (see #P0946)

Bitfields for Intel 82420EX turbo/reset control register:
Bit(s)	Description	(Table P0946)
 7-4	reserved (0)
 3	(450KX/GX only) enable CPU BIST on reset
 2	reset CPU
 1	reset mode
	0 soft reset
	1 hard reset
 0	deturbo mode
Note:	when resetting the CPU, two writes are required: the first sets the
	  state of bit 1 while keeping bit 2 cleared, and the second sets
	  bit 2; the reset occurs on bit 2's transition from 0 to 1.
SeeAlso: PORT C051h
----------P0CFB------------------------------
PORT 0CFB - Intel 82434NX (Neptune) - PCI MECHANISM CONTROL REGISTER
Note:	not present on the 82434LX (Mercury), which supports only mechanism #2
SeeAlso: PORT 0CF8h

0CFB  RW  specify which PCI access mechanism is to be enabled

Bitfields for Intel 82434NX PCI mechanism control register:
Bit(s)	Description	(Table P0947)
 7-1	reserved
 0	PCI Configuration Access Mechanism Select
	=0 use PCI configuration access mechanism #2 (0CF8/0CFA) (default)
	=1 use PCI configuration access mechanism #1 (0CF8/0CFC)
--------s-P0E800E83--------------------------
PORT 0E80-0E83 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:	dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
	  PORT 0E80h-0E83h, and PORT 0F40h-0F43h
--------s-P0E800E87--------------------------
PORT 0E80-0E87 - Windows Sound System
Range:	PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
--------V-P0EE8------------------------------
PORT 0EE8 - S3 86C928 video controller (ELSA Winner 1000)
--------V-P0EE80EEF--------------------------
PORT 0EE8-0EEF - 8514/A and compatible (e.g. ATI Graphics Ultra) - HSYNC WIDTH

0EE8w -W  CRT control: horizontal sync width
--------s-P0F400F43--------------------------
PORT 0F40-0F43 - Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:	dipswitch selectable from PORT 0530h-0533h, PORT 0604h-0607h,
	  PORT 0E80h-0E83h, and PORT 0F40h-0F43h
--------s-P0F400F47--------------------------
PORT 0F40-0F47 - Windows Sound System
Range:	PORT 0530h-0537h,PORT 0604h-060Bh,PORT 0E80h-0E87h,PORT 0F40h-0F47h
SeeAlso: PORT 0530h"Sound System"
--------s-P0F8D------------------------------
PORT 0F8D - OPTi 82C750 (Vendetta) - AUDIO MODULE BASE ADDRESS REGISTER
SeeAlso: PORT 0F8Eh,PORT 0530h"Vendetta"

0F8D  RW  "MCBase" base register (see #P0948)

Bitfields for OPTi "Vendetta" (82C750) audio module base register:
Bit(s)	Description	(Table P0948)
 7	index/data port access protection disable
 6-5	reserved
 4-0	index/data port address bits 8-4
	  (bits 15-9 = 0000111; bits 3-0 = 1110 for index port, data port +1)
SeeAlso: #P0949
----------P0F8E0F8F--------------------------
PORT 0F8E-0F8F - OPTi "Vendetta" (82C750) CHIPSET - Audio Module Data Registers
Range:	The I/O address range is selectable using port 0F8Dh from among
	  0ExE-0ExF and 0FxE-0FxF
SeeAlso: PORT 0F8Dh,PORT 0530h"Vendetta"

0F8E  RW  "MCIdx" index register (see #P0949)
0F8F  RW  "MCData" data register

(Table P0949)
Values for OPTi "Vendetta" (82C750) Audio Module configuration registers:
 00h	disable
 01h	base/type configuration register (see #P0950)
 02h	reserved
 03h	Sound Blaster/Windows Sound System configuration register (see #P0951)
 04h	user programmable general purpose register (see #P0952)
 05h	option register (see #P0953)
 06h	MIDI interface register (write-only) (see #P0954)
 07h	semaphore software register
 08h	reserved
 09h	test control register 1 (see #P0955)
 0Ah	test control register 2 (see #P0956)
 0Bh	status register (read-only) (see #P0957)
 0Ch	test register (see #P0958)
 0Dh	PNP status register (read-only) (see #P0959)
 0Eh	PNP card select number register (read-only)
 0Fh	PNP read port address register (read-only)
 10h	volume control register (see #P0960)
 11h	reserved (serial EEPROM)
 12h	CONFIG status register (see #P0961)
 13h	FM control register (see #P0962)
 14h	reserved (GPIO control)
 15h	serial audio control register 0 (see #P0963)
 16h	serial audio control register 1 (see #P0964)
 17h	reserved

Bitfields for OPTi "Vendetta" Audio Module base/type configuration register:
Bit(s)	Description	(Table P0950)
 7	Sound Blaster base I/O address
	0 = 220h
	1 = 240h
 6	reserved
 5-4	Windows Sound System base I/O address
	00 = 530h
	01 = E80h
	10 = F40h
	11 = 640h
 3-1	reserved
 0	game port enable
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module SB/WSS configuration register:
Bit(s)	Description	(Table P0951)
 7	reserved
 6	reserved (0 for normal WSS operation)
 5-3	digital audio processor IRQ
	000 = disable
	001 = IRQ7
	010-100 = IRQ9-IRQ11
	101 = IRQ5
	110-111 = reserved
 2-0	digital audio processor DMA
	000 = disable
	001-010 = QRQ0-DRQ1
	011 = DRQ3
	100 = disable, DRQ1 (if dual channel DMA mode)
	101 = DRQ0, DRQ1 (if dual channel DMA mode)
	110 = DRQ1, DRQ0 (if dual channel DMA mode)
	111 = DRQ3, DRQ0 (if dual channel DMA mode)
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module user programmable general purpose:
Bit(s)	Description	(Table P0952)
 7-6	playback FIFO flow
	00 = empty
	01 = full-2
	10 = full-4
	11 = not full
 5-4	OPL select
	00 = OPL2
	01 = OPL3
	10 = OPL4
	11 = OPL5
 3	D/A controller zero
	0 = hold
	1 = clear
 2	audio enable
 1-0	Sound Blaster version
	00 = 2.1
	01 = 1.5
	10 = 3.2
	11 = 4.4
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module option register:
Bit(s)	Description	(Table P0953)
 7-6	reserved
 5	codec expanded mode enable
	  (must be set to access expanded mode codec indirect registers
	  10h-1Fh)
 4	Sound Blaster ADPCM enable
 3	Sound Blaster command FIFO enable
 2	Sound Blaster Pro mixer voice volume emulation volume effect enable
 1	DMA watchdog timer enable
 0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module MIDI interface register:
Bit(s)	Description	(Table P0954)
 7	MPU-401 enable
 6-5	MPU-401 base address
	00 = 330h
	01 = 320h
	10 = 310h
	11 = 300h
 4-3	MPU-401 IRQ
	00 = IRQ9
	01 = IRQ10
	10 = IRQ5
	11 = IRQ7
 2	reserved
 1	Windows Sound System mode enable
 0	Sound Blaster mode enable
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module test control register 1:
Bit(s)	Description	(Table P0955)
 7	digital power-down
 6	analog power-down
 5-2	reserved
 1	software reset enable
 0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module test control register 2:
Bit(s)	Description	(Table P0956)
 7	playback reset
 6	capture reset
 3	PNP test
 2-0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module status register:
Bit(s)	Description	(Table P0957)
 7	playback DMA pending
 6	capture DMA pending
 5	MPU interrupt pending
 4	reserved
 3	capture interrupt pending
 2	playback interrupt pending
 1	playback FIFO empty
 0	capture FIFO empty
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module test register:
Bit(s)	Description	(Table P0958)
 7-5	reserved
 4	digital test output high/low byte (write-only)
 3-0	digital test output select (write-only)
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module PNP status register:
Bit(s)	Description	(Table P0959)
 7	CSN not 0, active high
	1 = CSN assigned by PNP configuration manager
 6-5	reserved
 4	audio module logical device enable
 3	1 = audio module PNP logic in CONFIG mode
 2	1 = audio module PNP logic in ISOLATE mode
 1	1 = audio module PNP logic in SLEEP mode
 0	1 = audio module PNP logic in WAIT4KEY mode
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module volume control register:
Bit(s)	Description	(Table P0960)
 7-4	reserved
 3	master volume mute
 2-0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module CONFIG status register:
Bit(s)	Description	(Table P0961)
 7	reserved
 6	ASIO enable
 5-4	reserved
 3-0	chip revision ID (read-only)
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module FM control register:
Bit(s)	Description	(Table P0962)
 7-3	reserved
 2	mega bass enable
 1	enhanced FM feature OPTi mode enable
 0	external FM enable
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module serial audio control register 0:
Bit(s)	Description	(Table P0963)
 7-6	FDAC clock controller
	00 = reserved
	01 = internal FM
	10 = reserved
	11 = external serial audio
 5-2	reserved
 1	FDAC data
	0 = internal FM
	1 = external serial audio
 0	reserved
SeeAlso: #P0949

Bitfields for OPTi "Vendetta" Audio Module serial audio control register 1:
Bit(s)	Description	(Table P0964)
 7	ASIO reset
 6	ASIO test
 5-4	reserved
 3	SCLK polarity
	0 = reverse
	1 = no change
 2	FSYNC polarity
	0 = reverse
	1 = no change
 1-0	reserved
SeeAlso: #P0949
----------P0xx00xxF--------------------------
PORT 0xx0-0xxF - Intel 82595TX - ISA/PCMCIA Ethernet Controller
Range:	at any multiple of 16 in first 1024 I/O addresses

+000  RW  command register (see #P0965)
--- I/O bank 0 ---
+001  RW  status register (see #P0966)
+002  RW  id register (see #P0967)
+003  RW  mask register (see #P0968)
+004  RW  RCV CAR/BAR low
+005  RW  RCV CAR/BAR high
+006  RW  RCV STOP REG low
+007  RW  RCV STOP REG high
+008  RW  RCV copy treshold REG
+009  RW  reserved
+00A  RW  XMT CAR/BAR low
+00B  RW  XMT CAR/BAR high
+00C  RW  host address reg/32-bit I/O (byte 0) low
+00D  RW  host address reg/32-bit I/O (byte 1) high
+00E  RW  local memory/32-bit I/O (byte 2) IO port low