fsm2_in.v

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module fsm2_in(clock, reset, enter, halt, input1, output1);
input clock;
input reset;
input enter;
input [15:0]input1;
output halt;
reg halt;
output[15:0]output1;
reg [3:0]state;
reg[15:0]IR;
reg[4:0]PC;
reg[15:0]A;
reg[4:0]memory_address;
//define states
`define s_start 0
`define s_fetch 1
`define s_decode 2
`define s_load 3
`define s_add 4
`define s_sub 5
`define s_store 6
`define s_input 7
`define s_halt 15
assign output1 = A;
// Single Port ROM
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 5;

// Declare the ROM variable
	reg [DATA_WIDTH-1:0]memory_data[2**ADDR_WIDTH-1:0];
	/*initial
	begin
		$readmemb("Text1.txt", memory_data);
	end*/
//*********************************************
always @(posedge clock or posedge reset)
begin
if (reset) begin
			PC=5'b0;
			IR=16'b0;
			A=16'b0;
			halt=1'b0;
			$readmemb("Text1.txt", memory_data);
			state = `s_start;
			end
else 	begin
			case (state)
				`s_start: 
					begin
					memory_address = PC;
					state = `s_fetch;
					end
				`s_fetch:
					begin
					IR = memory_data[memory_address];
					PC = PC + 5'b1;
					state = `s_decode;
					end
				`s_decode:
					begin
					memory_address = IR[4:0];
					case (IR[15:12])
					4'b0000: state = `s_load;
					4'b0001: state = `s_add;
					4'b0010: state = `s_sub;
					4'b0011: state = `s_store;
					4'b0100: state = `s_input;
					4'b1111: state = `s_halt;
					default: state = `s_start;
					endcase
					end
				`s_load:
					begin
					A = memory_data[memory_address];
					state = `s_start;
					end
				`s_add:
					begin
					A = A + memory_data[memory_address];
					state = `s_start;
					end
				`s_sub:
					begin
					A = A - memory_data[memory_address];
					state = `s_start;
					end
				`s_store:
					begin
					memory_data[memory_address] = A;
					state = `s_start;
					end
				`s_input:
					begin
					A = input1;
					if (enter == 0) state = `s_input;
					else state = `s_start;
					end
				`s_halt:
					begin
					halt = 1'b1;
					state = `s_halt;
					end
				default:
					state = `s_halt;
			endcase
		end
end
endmodule