📄 cdma32.mdl
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SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [220, 171, 260, 209]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "1"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType Gain
Name "Gain"
Position [195, 23, 235, 57]
ShowName off
Gain "0.0330"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain1"
Position [125, 91, 165, 129]
ShowName off
Gain "5.5513e-004"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "Out1"
Position [435, 108, 465, 122]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "In1"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -70]
DstBlock "Gain"
DstPort 1
}
Branch {
DstBlock "Gain1"
DstPort 1
}
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [-35, 0; 0, -65]
DstBlock "Add"
DstPort 2
}
Line {
SrcBlock "Add"
SrcPort 1
Points [0, 0; 45, 0]
Branch {
Points [0, 70]
DstBlock "Delay"
DstPort 1
}
Branch {
DstBlock "Add1"
DstPort 2
}
}
Line {
SrcBlock "Add1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [85, 0; 0, 65]
DstBlock "Add1"
DstPort 1
}
Line {
SrcBlock "Gain1"
SrcPort 1
DstBlock "Add"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "PN Sequence\nGenerator"
Ports [0, 1]
Position [155, 447, 225, 483]
ShowName off
SourceBlock "commseqgen2/PN Sequence\nGenerator"
SourceType "PN Sequence Generator"
poly "[1 0 0 0 0 1 1]"
ini_sta "[0 0 0 0 0 1]"
shift "0"
Ts "1e-6"
frameBased on
sampPerFrame "63"
reset off
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [515, 132, 545, 163]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [520, 377, 550, 408]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product3"
Ports [2, 1]
Position [200, 367, 230, 398]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product4"
Ports [2, 1]
Position [645, 247, 675, 278]
Orientation "left"
NamePlacement "alternate"
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product5"
Ports [2, 1]
Position [200, 122, 230, 153]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Raised Cosine\nReceive Filter"
Ports [1, 1]
Position [315, 118, 395, 162]
ShowName off
SourceBlock "commfilt2/Raised Cosine\nReceive Filter"
SourceType "Raised Cosine Receive Filter"
ShowPortLabels on
filtType "Square root"
N "9"
D "4"
R "0.2"
sampMode "Frame-based"
rateMode "Downsampling"
downFactor "9"
downOffset "0"
checkGain "Normalized"
filterGain "1"
checkCoeff off
variableName "rcRxFilt"
launchFVT off
}
Block {
BlockType Reference
Name "Raised Cosine\nReceive Filter1"
Ports [1, 1]
Position [315, 363, 395, 407]
ShowName off
SourceBlock "commfilt2/Raised Cosine\nReceive Filter"
SourceType "Raised Cosine Receive Filter"
ShowPortLabels on
filtType "Square root"
N "9"
D "4"
R "0.2"
sampMode "Frame-based"
rateMode "Downsampling"
downFactor "9"
downOffset "0"
checkGain "Normalized"
filterGain "1"
checkCoeff off
variableName "rcRxFilt1"
launchFVT off
}
Block {
BlockType Sum
Name "Sum of\nElements"
Ports [1, 1]
Position [600, 135, 630, 165]
ShowName off
Inputs "+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum of\nElements1"
Ports [1, 1]
Position [600, 380, 630, 410]
ShowName off
Inputs "+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "Out1"
Position [820, 328, 850, 342]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Sum of\nElements"
DstPort 1
}
Line {
SrcBlock "Sum of\nElements"
SrcPort 1
Points [70, 0; 0, 105]
DstBlock "Product4"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [70, 0]
Branch {
Points [0, -135]
DstBlock "Product5"
DstPort 1
}
Branch {
Points [0, 125]
DstBlock "Product3"
DstPort 2
}
}
Line {
SrcBlock "Product5"
SrcPort 1
DstBlock "Raised Cosine\nReceive Filter"
DstPort 1
}
Line {
SrcBlock "Product2"
SrcPort 1
DstBlock "Sum of\nElements1"
DstPort 1
}
Line {
SrcBlock "Sum of\nElements1"
SrcPort 1
Points [70, 0; 0, -125]
DstBlock "Product4"
DstPort 2
}
Line {
SrcBlock "Discrete-Time\nVCO2"
SrcPort 1
DstBlock "Buffer1"
DstPort 1
}
Line {
SrcBlock "Buffer1"
SrcPort 1
Points [-25, 0; 0, -85]
DstBlock "Product5"
DstPort 2
}
Line {
SrcBlock "Discrete-Time\nVCO4"
SrcPort 1
DstBlock "Buffer2"
DstPort 1
}
Line {
SrcBlock "Buffer2"
SrcPort 1
Points [-20, 0; 0, 75]
DstBlock "Product3"
DstPort 1
}
Line {
SrcBlock "Product4"
SrcPort 1
DstBlock "Loop Filter"
DstPort 1
}
Line {
SrcBlock "Loop Filter"
SrcPort 1
Points [-10, 0]
Branch {
Points [-15, 0]
Branch {
Points [0, -35]
DstBlock "Discrete-Time\nVCO2"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Discrete-Time\nVCO4"
DstPort 1
}
}
Branch {
Points [0, 70]
DstBlock "Abs"
DstPort 1
}
}
Line {
SrcBlock "Abs"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Product3"
SrcPort 1
DstBlock "Raised Cosine\nReceive Filter1"
DstPort 1
}
Line {
SrcBlock "PN Sequence\nGenerator"
SrcPort 1
DstBlock "BPSK\nModulator\nBaseband1"
DstPort 1
}
Line {
SrcBlock "BPSK\nModulator\nBaseband1"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [20, 0; 0, -65]
Branch {
Points [0, -245]
DstBlock "Product"
DstPort 2
}
Branch {
DstBlock "Product2"
DstPort 2
}
}
Line {
SrcBlock "Raised Cosine\nReceive Filter1"
SrcPort 1
DstBlock "Product2"
DstPort 1
}
Line {
SrcBlock "Raised Cosine\nReceive Filter"
SrcPort 1
DstBlock "Product"
DstPort 1
}
}
}
Line {
SrcBlock "frequency-syn"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
DstBlock "BPSK\nModulator\nBaseband2"
DstPort 1
}
Line {
SrcBlock "PN Sequence\nGenerator"
SrcPort 1
DstBlock "BPSK\nModulator\nBaseband1"
DstPort 1
}
Line {
SrcBlock "BPSK\nModulator\nBaseband1"
SrcPort 1
Points [45, 0; 0, -35]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "BPSK\nModulator\nBaseband2"
SrcPort 1
Points [45, 0; 0, 40]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Raised Cosine\nTransmit Filter"
DstPort 1
}
Line {
SrcBlock "Sine Wave"
SrcPort 1
Points [40, 0; 0, -35]
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Product1"
SrcPort 1
Points [35, 0]
DstBlock "AWGN\nChannel"
DstPort 1
}
Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
DstBlock "frequency-syn"
DstPort 1
}
Line {
SrcBlock "Raised Cosine\nTransmit Filter"
SrcPort 1
Points [15, 0; 0, 25]
DstBlock "Product1"
DstPort 1
}
}
}
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