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ZeroCross on
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Block {
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SourceBlock "dspbuff3/Buffer"
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V "0"
ic "0"
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BlockType Reference
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Orientation "down"
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"\nTo Constant"
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SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop "<"
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LogicOutDataTypeMode "boolean"
ZeroCross off
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BlockType Constant
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Block {
BlockType Reference
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Position [325, 297, 415, 343]
Orientation "left"
NamePlacement "alternate"
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FontName "Arial"
SourceBlock "commsynccomp2/Discrete-Time\nVCO"
SourceType "Discrete-Time VCO"
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SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "30000"
Kc "1"
Ph "pi/2"
ts "1e-6"
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Block {
BlockType Reference
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Position [325, 352, 415, 398]
Orientation "left"
NamePlacement "alternate"
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FontName "Arial"
SourceBlock "commsynccomp2/Discrete-Time\nVCO"
SourceType "Discrete-Time VCO"
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SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "30000"
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ts "1e-6"
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Orientation "left"
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OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
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Block {
BlockType Reference
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SourceType "PN Sequence Generator"
poly "[6 5 0]"
ini_sta "[0 0 1 0 0 1]"
shift "0"
Ts "1e-6"
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InputSameDT off
OutDataTypeMode "Inherit via internal rule"
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Block {
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Name "Real-Imag to\nCompex"
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Orientation "up"
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Inputs "+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
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Block {
BlockType Reference
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SourceBlock "commutil2/Unipolar to\nBipolar\nConverter"
SourceType "Unipolar to Bipolar Converter"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
M "2"
polarity "Negative"
dataType "Same as input"
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Block {
BlockType Outport
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Position [780, 433, 810, 447]
IconDisplay "Port number"
BusOutputAsStruct off
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DstBlock "Sum of\nElements"
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DstBlock "Compare\nTo Constant"
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DstBlock "Product1"
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Line {
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DstBlock "Real-Imag to\nCompex"
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SrcBlock "Real-Imag to\nCompex"
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DstBlock "Product2"
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DstBlock "Real-Imag to\nCompex"
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Line {
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DstBlock "Unipolar to\nBipolar\nConverter"
DstPort 1
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DstBlock "Product1"
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SrcBlock " "
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Branch {
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Branch {
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DstBlock "Discrete-Time\nVCO"
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Branch {
Points [0, 25]
DstBlock "Discrete-Time\nVCO1"
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Branch {
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Line {
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}
Line {
SrcBlock "Abs1"
SrcPort 1
DstBlock "Gain1"
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}
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Line {
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SrcPort 1
DstBlock "BPSK\nModor\nBaseband"
DstPort 1
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Line {
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SrcPort 1
DstBlock "frequency-syn"
DstPort 1
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SrcBlock "PN Sequence1"
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DstBlock "Unipolar to\nBipolar\nConverter"
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DstBlock "Product"
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Points [30, 0; 0, -30]
DstBlock "Product"
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Line {
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SrcPort 1
DstBlock "AWGN\nChannel"
DstPort 1
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Line {
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SrcPort 1
DstBlock "FE"
DstPort 1
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Line {
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SrcPort 1
Points [15, 0; 0, 20]
DstBlock "Real-Imag to\nComplex"
DstPort 1
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Points [15, 0; 0, -20]
DstBlock "Real-Imag to\nComplex"
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DstPort 1
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Points [20, 0; 0, -105]
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