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}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Constant
}
Block {
BlockType Display
Format "short"
Decimation "10"
Floating off
SampleTime "-1"
}
Block {
BlockType FrameConversion
OutFrame "Frame based"
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Math
Operator "exp"
OutputSignalType "auto"
SampleTime "-1"
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Reshape
OutputDimensionality "1-D array"
OutputDimensions "[1,1]"
}
Block {
BlockType Rounding
Operator "floor"
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "bpsk"
Location [2, 82, 1270, 753]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [510, 121, 605, 179]
SourceBlock "commchan3/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "2000"
noiseMode "Signal to noise ratio (Eb/No)"
EbNodB "EBNO"
EsNodB "10"
SNRdB "0"
bitsPerSym "1"
Ps "1"
Tsym "0.0001"
variance "1"
}
Block {
BlockType Reference
Name "BPSK\nDemodulator\nBaseband"
Ports [1, 1]
Position [895, 195, 970, 245]
DialogController "commDDGCreate"
DialogControllerArgs "DataTag0"
SourceBlock "commdigbbndpm3/BPSK\nDemodulator\nBaseband"
SourceType "BPSK Demodulator Baseband"
Ph "0"
DecType "Hard decision"
VarSource "Dialog"
Variance "1"
outDtype "double"
}
Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband"
Ports [1, 1]
Position [275, 126, 350, 174]
SourceBlock "commdigbbndpm3/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ph "0"
outDtype "double"
outWordLen "16"
outUDDataType "sfix(16)"
outFracLenMode "Best precision"
outFracLen "15"
}
Block {
BlockType Display
Name "Display3"
Ports [1]
Position [1110, 52, 1190, 178]
Decimation "1"
Lockdown off
}
Block {
BlockType Product
Name "Divide"
Ports [2, 1]
Position [830, 200, 860, 235]
Inputs "**"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2, 1]
Position [1005, 87, 1080, 138]
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop on
numErr "1e6"
maxBits "1e6"
}
Block {
BlockType Reference
Name "Insert Zero"
Ports [1, 1]
Position [160, 128, 240, 172]
SourceBlock "commsequence2/Insert Zero"
SourceType "Insert Zero"
insertZeroVector "[1 1 0 1 1].'"
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [1, 1]
Position [765, 209, 795, 241]
Operator "conj"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel"
Ports [1, 1]
Position [385, 121, 480, 179]
SourceBlock "commchan3/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
maxDopplerShift "100"
pathDelays "[0]"
avgPathGaindB "[0]"
normalizePathGains on
seed "2000"
enableProbe "0"
openVisAtStart off
outPathGains off
outDelay off
}
Block {
BlockType Reference
Name "Puncture1"
Ports [1, 1]
Position [655, 128, 735, 172]
SourceBlock "commsequence2/Puncture"
SourceType "Puncture"
punctureVector "[1 1 0 1 1].'"
}
Block {
BlockType Reference
Name "Puncture2"
Ports [1, 1]
Position [655, 203, 735, 247]
SourceBlock "commsequence2/Puncture"
SourceType "Puncture"
punctureVector "[0 0 1 0 0].'"
}
Block {
BlockType Reference
Name "Random Integer\nGenerator"
Ports [0, 1]
Position [30, 128, 110, 172]
SourceBlock "commrandsrc2/Random Integer\nGenerator"
SourceType "Random Integer Generator"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
mul "2"
seed "70"
Ts "0.0001"
frameBased on
sampPerFrame "4"
orient off
outDataType "double"
}
Line {
SrcBlock "BPSK\nModulator\nBaseband"
SrcPort 1
DstBlock "Multipath Rayleigh\nFading Channel"
DstPort 1
}
Line {
SrcBlock "Puncture1"
SrcPort 1
Points [75, 0]
DstBlock "Divide"
DstPort 1
}
Line {
SrcBlock "Divide"
SrcPort 1
DstBlock "BPSK\nDemodulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "Error Rate\nCalculation"
SrcPort 1
DstBlock "Display3"
DstPort 1
}
Line {
SrcBlock "Multipath Rayleigh\nFading Channel"
SrcPort 1
DstBlock "AWGN\nChannel"
DstPort 1
}
Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
Points [20, 0]
Branch {
DstBlock "Puncture1"
DstPort 1
}
Branch {
Points [0, 75]
DstBlock "Puncture2"
DstPort 1
}
}
Line {
SrcBlock "BPSK\nDemodulator\nBaseband"
SrcPort 1
Points [0, -95]
DstBlock "Error Rate\nCalculation"
DstPort 2
}
Line {
SrcBlock "Puncture2"
SrcPort 1
DstBlock "Math\nFunction"
DstPort 1
}
Line {
SrcBlock "Random Integer\nGenerator"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Insert Zero"
DstPort 1
}
Branch {
Points [0, -50]
DstBlock "Error Rate\nCalculation"
DstPort 1
}
}
Line {
SrcBlock "Insert Zero"
SrcPort 1
DstBlock "BPSK\nModulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "Math\nFunction"
SrcPort 1
DstBlock "Divide"
DstPort 2
}
}
}
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NumRecords 1
DataRecord {
Tag DataTag0
Data " %)30 . < 8 ( 0 % "
"\" $ ! 0 . 0 8 ( ! % \" $ "
"/ 0 0 #P $)04TM$96UO9'5L871O<@ "
}
}
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