_start.s

来自「Centrality Atlas II development software」· S 代码 · 共 486 行

/*
 * $QNXLicenseC: 
 * Copyright 2007,2008, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */



/*
 * Reset code for Centrality Atlas-II Development Board, with ARM 926EJ-S Core
 */

#include "atlasii.h"
#define CPSR_MASK           	0x1F
#define CPSR_SVC_IF       	0xD3
#define MMU_I                  	0x1000

.macro LED1out val
      mov r6, \val
      ldr	r7, =0x14000A00
      strb	r6, [r7]
.endm
.macro LED2out val
      mov r6, \val
      ldr	r7, =0x14000C00
      strb	r6, [r7]
.endm

    .text
    .align 4
    .globl  _start
    .globl  XipClkSwitch
    .globl ARMReadCacheInfo
    .globl LockCache
    .globl FlushICache
_start:
        /*
         * Make sure we're in SVC_32 mode, and the MMU is off
         */
        mrs                lr, cpsr
        bic                lr, lr, #CPSR_MASK
        orr                lr, lr, #CPSR_SVC_IF
        msr                cpsr_all, lr

        mov                r0, #0
        mcr                p15, 0, r0, c1, c0, 0


      # RISCINT_WAIT1 += 0x01010101
      mov r0, #0x90000000
      ldr r1, [r0, #0x10]
      ldr r2, =0x01010101
      add r1, r1, r2
      str r1, [r0, #0x10]

      #; ;;RISCINT_WAIT2 += 0x01010101
      #; RISCINT_WAIT2 += 0x02020202
      ldr r1, [r0, #0x14]
      ldr r2, =0x01010101
      add r1, r1, r2
      str r1, [r0, #0x14]

	/*	PWR_DELAY_CTRL0 = (PWR_DELAY_CTRL0 & ~0x0ffff) | 0x280a; */
	ldr r0, =0x9006004c
	ldr	r1, [r0]
	bic r1, r1, #0xff
	bic r1, r1, #0xff00
	orr r1, r1, #0x2800
	orr r1, r1, #0x0a
	str r1, [r0]

	
	/*********************************
	* To enable rom boot for ddr,
	* we need to config CS0 first
	* and then turn on pll
	*********************************/
	#  ROM_CFG_CS0=0x034C0C00; // 8  bits rom controller interface;
	ldr r0, =0xa0010000
	ldr r1, =0x034f4f00
	str r1, [r0]

	#  ROM_CFG_CS1=0x214C0C00; // 8  bits rom controller interface;
	ldr r1, =0x214f4f00
	str r1, [r0, #4]

	LED1out #0x79
	LED2out #0x79

	/*********************************
	* for each dram type, we have 
	* different settings
	* and bootup sequence
	***********************************/
	ldr r0, =_POWER_MODULE_BASE
	ldr r1, [r0, #PWR_PAD_CTRL_OFFSET]
	and r1, r1, #3
	cmp r1, #1
	bne setsdr

	# SM_WAIT = 0x1878
	ldr r0, =0x80070004
	ldr r1, =0x1878
	str r1, [r0]

#if defined(DRAM_TYPE_DDR16)
	# Config Power Manager Registers
	ldr r0, =_POWER_MODULE_BASE
	ldr r2, [r0, #PWR_CLK_ENABLE_OFFSET]
	mov r1, #0x4
	orr r1, r1, r2
	str r1, [r0, #PWR_CLK_ENABLE_OFFSET]

	ldr r1, =0x420
	str r1, [r0, #PWR_PLL1_CONFIG_OFFSET]   //408MHz
	ldr r1, =0xfff8444
	str r1, [r0, #PWR_CLK_RATIO_OFFSET]
	mov r1, #0x100000
30:
	subs r1, r1, #1
	bgt  30b
	ldr r1, =SYS_CS_PLL1
	str r1, [r0, #PWR_CLK_SWITCH_OFFSET]

	mov r1, #0x400
31:
	subs r1, r1, #1
	bgt  31b
	ldr r1, =0x20202606
	str r1, [r0, #PWR_DELAY_CTRL0_OFFSET]

	# Config Memory Controller Registers
       mov r0, #MEM_CONTROL_BASE
       ldr r1, =0x00000940
       str r1, [r0, #MEMC_TYPE_OFFSET]
       ldr r1, =0x3f226168
       str r1, [r0, #MEMC_TIMING_OFFSET]
       ldr r1, =0x13f000
       str r1, [r0, #MEMC_PWR_OFFSET]
       ldr r1, =0x23
       str r1, [r0, #MEMC_MODE_OFFSET]
       ldr r1, =0x00002000
       str r1, [r0, #MEMC_EXTEND_OFFSET]
       ldr r1, =0x6
       str r1, [r0, #MEMC_START_OFFSET]
#else
	ldr r0, =PLL1_300M
	ldr r1, =0xfff4221
	bl XipClkSwitch

    	ldr r2, =_POWER_MODULE_BASE
    	ldr r3, =0xf170a
    	str r3, [r2, #PWR_DELAY_CTRL0_OFFSET]

    	# Config Memory Controller Registers
      	mov r0, #MEM_CONTROL_BASE

    	ldr r1, =0x00000B40
    	str r1, [r0, #MEMC_TYPE_OFFSET]

    	ldr r1, =0x2a1620d1
    	str r1, [r0, #MEMC_TIMING_OFFSET]

    	ldr r1, =0x181000
    	str r1, [r0, #MEMC_PWR_OFFSET]

    	ldr r1, =0x22
    	str r1, [r0, #MEMC_MODE_OFFSET]

    	ldr r1, =0x00002000
   	str r1, [r0, #MEMC_EXTEND_OFFSET]

    	ldr r1, =0x6
    	str r1, [r0, #MEMC_START_OFFSET]
#endif
    	b	memdone

setsdr:
#Set default CLOCK SDR_276_184_92_92_CLOCK
	ldr r2, =_SMDF_MODULE_BASE
	ldr r0, =0x1878
	str r0, [r2, #4]
	ldr r0, [r2, #0x28]
	orr r0, r0, #1
	str r0, [r2, #0x28]

	mov r0, #3
	str r0, [r2, #0xF00]
	mov r0, #0
	str r0, [r2, #0xF04]
	mov r0, #1
	str r0, [r2, #0xF10]

	ldr r2, =0xb0000810  //set IOBG_ARB_CLKRATIO=0
	mov r0, #0
	str r0, [r2]
	ldr r2, =0x90000018 //set RISCINT_WIDTH=0
	str r0, [r2]
	
	ldr r2, =_POWER_MODULE_BASE
	ldr r0, =0x0015
	ldr r1, =0xfff6632
    	str r0, [r2, #PWR_PLL1_CONFIG_OFFSET]
    	str r1, [r2, #PWR_CLK_RATIO_OFFSET]

    	mov r3, #1000
222:
    	subs r3, r3, #1
    	bgt  222b

    	ldr r3, =SYS_CS_PLL1
    	str r3, [r2, #PWR_CLK_SWITCH_OFFSET]

    	mov r3, #1000
233:
    	subs r3, r3, #1
    	bgt  233b
	
	LED1out #0x19
	LED2out #0x19
	
#if defined(DRAM_TYPE_SDR16)
    #
    # Config Power Manager Registers
    #
    ldr r0, =_POWER_MODULE_BASE

    ldr r1, =0x01031a0a
    str r1, [r0, #PWR_DELAY_CTRL0_OFFSET]

    ldr r1, =0x180f0f0f
    str r1, [r0, #PWR_DELAY_CTRL1_OFFSET]

    mov r0, #MEM_CONTROL_BASE

    ldr r1, =0x00000140
    str r1, [r0, #MEMC_TYPE_OFFSET]

    ldr r1, =0x3F226168
    str r1, [r0, #MEMC_TIMING_OFFSET]

    ldr r1, =0x00125000
    str r1, [r0, #MEMC_PWR_OFFSET]

    ldr r1, =0x23
    str r1, [r0, #MEMC_MODE_OFFSET]

    ldr r1, =0x2000
    str r1, [r0, #MEMC_EXTEND_OFFSET]

    ldr r1, =0x6
    str r1, [r0, #MEMC_START_OFFSET]

    ldr r0, =_POWER_MODULE_BASE
    ldr r1, =0x0
    str r1, [r0, #PWR_SLEEP_STATUS_OFFSET]  ; disable dram hold

    # RISCINT_PREFETCH_EN = 0x00
    mov r0, #0x90000000
    ldr r1, =0x0
    str r1, [r0, #0x24]

#else
    #
    # Config Power Manager Registers
    #
    ldr r0, =_POWER_MODULE_BASE

    ldr r1, =0x0103100a
    str r1, [r0, #PWR_DELAY_CTRL0_OFFSET]

    ldr r1, =0x280f0f0f
    str r1, [r0, #PWR_DELAY_CTRL1_OFFSET]

    #
    # Config Memory Controller Registers
    #
    mov r0, #MEM_CONTROL_BASE

    ldr r1, =0x00000340
    str r1, [r0, #MEMC_TYPE_OFFSET]

    ldr r1, =0x3F2240D1
    str r1, [r0, #MEMC_TIMING_OFFSET]

    ldr r1, =0x00024000
    str r1, [r0, #MEMC_PWR_OFFSET]

    ldr r1, =0x22
    str r1, [r0, #MEMC_MODE_OFFSET]

    ldr r1, =0x2000
    str r1, [r0, #MEMC_EXTEND_OFFSET]

    ldr r1, =0x6
    str r1, [r0, #MEMC_START_OFFSET]

    ldr r0, =_POWER_MODULE_BASE
    ldr r1, [r0, #PWR_SLEEP_STATUS_OFFSET]
    and r1, r1, #0x10                       // set flash hold bit and clear any other bits
    str r1, [r0, #PWR_SLEEP_STATUS_OFFSET]  // disable dram hold

    # RISCINT_PREFETCH_EN = 0x01     // turn-on prefetch buffer in RISC interface
    mov r0, #0x90000000
    ldr r1, =0x1
    str r1, [r0, #0x24]
    
#endif

    /*------------------------*
    * DRAM configuration ends*
     -----------------------*/

memdone:
        
   # Determine which reset is it from...  PWR_SLEEP_STATUS
	ldr r0,=_POWER_MODULE_BASE
	ldrb r1,[r0, #PWR_SLEEP_STATUS_OFFSET]
	mov	r10, r1								// save the status for testing whether we
	and r1, r1, #0x17						// were in Sleep mode later in the code.
	str	r1, [r0, #PWR_SLEEP_STATUS_OFFSET]	// then write a zero clear the sleep status bit

	
	/*------------------------------------------------------*
	 * Enable I-cache                                       *
 	 *------------------------------------------------------*/
	mov		r0, #0
	mcr 		p15, 0x0, r0, c7, c10, 4		//Drain write buffer
	nop
	nop
	nop
	mcr		p15, 0x0, r0, c7, c5, 0x0				/* first invalidate entire instruction-cache */
	nop
	nop
	nop
	nop

	mrc		p15, 0x0, r1, c1, c0, 0x0				/* read control register 1 */
	orr		r1, r1, #0x1000							/* set I bit (enable Instruction-cache) */
	nop
	mcr		p15, 0x0, r1, c1, c0, 0x0				/* write back modified control register */
	nop
	nop
	nop
	nop

	ldr	r0, =0x4000  //16K 
	ldr	r1, =0x00000000
	ldr	r2, =0xC0000000
CopyLoop:
        ldr     r3, [r1], #4
        str     r3, [r2], #4
        subs   r0, r0, #4
        bne         CopyLoop

	LED1out #0x40
	LED2out #0x40

        /*
         * Jump to SDRAM
         */
        ldr                r3, =0x00003FFF
        and                r3, r3, pc
        orr                pc, r3, #0xC0000000

	
	/*------------------------------------------------------*
     	* Set up stack pointer and jump to C main()            *
 	 *------------------------------------------------------*/
	mov		sp, #0x0000E000 
	orr		sp, sp, #0xC0000000
	bl		main
	b		_start

    /*
    * XipClkSwitch
    * parameters:
    *		r0 -> pwr_pll1_config register value to be set
    *		r1 -> pwr_clk_ratio register value to be set
    * return: none
    */
XipClkSwitch:
   	# Config Power Manager Registers
	ldr r2, =_POWER_MODULE_BASE

	# switch to XTAL first
	ldr r3, [r2, #PWR_CLK_SWITCH_OFFSET]
	cmp r3, #0
	beq 21f

    	mov r3, #0
    	str r3, [r2, #PWR_CLK_SWITCH_OFFSET]

    	mov r3, #100
20:
    	subs r3, r3, #1
    	bgt  20b

21:
    	str r0, [r2, #PWR_PLL1_CONFIG_OFFSET]
    	str r1, [r2, #PWR_CLK_RATIO_OFFSET]

    	mov r3, #1000
22:
    	subs r3, r3, #1
    	bgt  22b

    	ldr r3, =SYS_CS_PLL1
    	str r3, [r2, #PWR_CLK_SWITCH_OFFSET]

    	mov r3, #1000
23:
    	subs r3, r3, #1
    	bgt  23b

	bx	lr
	
ARMReadCacheInfo:
    mrc     p15, 0, r0, c0, c0, 1   // read the cache info register

	bx lr

LockCache:       
        mrs	r3, spsr
        orr r3, r3, #0xc0
        msr spsr_cxsf, r3
            
        cmp r1, #0
        beq	unlock
        
        tst r2, #0x01
        beq	exit
                
        mrc p15, 0, r3, c9, c0, 1
        bic r3, r3, #0xf
        orr r3, r3, #0xe
        mcr p15, 0, r3, c9, c0, 1
        ldr r10, =128 // ;[r4, #L1ISetsPerWay]

10:        
        mcr p15, 0, r0, c7, c5, 1
        mcr p15, 0, r0, c7, c13, 1
        add r0, r0, #32
        subs r10, r10, #1
        bgt 10b
        
        mrc p15, 0, r3, c9, c0, 1
        bic r3, r3, #0xe
        orr r3, r3, #1
        mcr p15, 0, r3, c9, c0, 1

        b exit    

unlock:
		mrc p15, 0, r3, c9, c0, 1
        bic r3, r3, #0xf
        mcr p15, 0, r3, c9, c0, 1
exit:       
        mrs	r3, spsr
        bic r3, r3, #0xc0
        msr spsr_cxsf, r3
        
        bx lr

FlushICache:        
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0
        
        bx lr