seratlasii.c

来自「Centrality Atlas II development software」· C语言 代码 · 共 115 行

/*
 * $QNXLicenseC: 
 * Copyright 2007,2008, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */





#include "ipl.h"
#include <hw/inout.h>
#include "atlasii.h"

static unsigned char	seratlasii_pollkey();
static unsigned char	seratlasii_getchar();
static void			seratlasii_putchar(unsigned char);

static const ser_dev atlasii_dev = {
	seratlasii_getchar,
	seratlasii_putchar,
	seratlasii_pollkey
};

static unsigned char seratlasii_pollkey(void)
{
	if (UART_RXFIFO_STATUS & UART_RXFIFO_EMPTY) 
		return 0;
	else
		return 1;
}

static unsigned char seratlasii_getchar(void)
{
	/*
	 * wait for data to be available	
	 */
	
	while (!seratlasii_pollkey())
		;

	return ((unsigned char) UART_RXFIFO_DATA);
}

static void seratlasii_putchar(unsigned char data)
{
	while (UART_TXFIFO_STATUS & UART_TXFIFO_FULL) {}
	UART_TXFIFO_DATA = data;
}

void
init_seratlasii(unsigned address, unsigned baud, unsigned clk, unsigned divisor)
{
    unsigned i,uart_baud_rate;

    clk=(clk<<1);

    for(uart_baud_rate=0, baud*=divisor; clk>=baud; uart_baud_rate++)
		clk-=baud;
	if((clk<<1)>=baud)
		uart_baud_rate++;

   	uart_baud_rate=(uart_baud_rate>>1)-1;

   	// for safety reason, reset the uart block
   	PWR_CLOCK_ENABLE(PWRCLK_SP0_EN);
   	RESET_DECLARE(RESET_SR_SP0_RST);
   	for(i=0; i<10; i++);
   	RESET_CLEAR(RESET_SR_SP0_RST);
   	for(i=0; i<10; i++);
   	ENABLE_USP0_DATA_PAD();// release pin to USP0 txd and rxd
   	ENABLE_USP0_CTRL_PAD();// release pin to USP0 flow control

	UART_DIVISOR = uart_baud_rate |((divisor-1)<<16);
	UART_LINE_CTRL = 3;
	UART_TX_DMA_IO_CTRL = UART_TX_IO_MODE;
	UART_RX_DMA_IO_CTRL = UART_RX_IO_MODE;
	UART_TX_DMA_IO_LEN = 0;
	UART_RX_DMA_IO_LEN = 0;
	UART_TXFIFO_CTRL = 0x08 ;
	UART_RXFIFO_CTRL = 0x18 ;
	UART_TXFIFO_LEVEL_CHK = 0x06 | (0x04 << 10) | (0x02 << 20);
	UART_RXFIFO_LEVEL_CHK = 0x02 | (0x04 << 10) | (0x06 << 20);
	UART_TXRX_ENA_REG = UART_RX_EN | UART_TX_EN;
	// Fifo Reset
	UART_TXFIFO_OP = UART_TXFIFO_RESET;
	UART_RXFIFO_OP = UART_RXFIFO_RESET;
	// Fifo Start
	UART_TXFIFO_OP = UART_TXFIFO_START;
	UART_RXFIFO_OP = UART_RXFIFO_START;
	// clear all pending uart interrupts
	UART_INT_STATUS = UART_INT_MASK_ALL;	
	
	/*
	 * Register our debug functions
	 */
	init_serdev((ser_dev *)&atlasii_dev);
}