init.c

来自「Centrality Atlas II development software」· C语言 代码 · 共 204 行

/*
 * $QNXLicenseC: 
 * Copyright 2007,2008, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


#include <hw/inout.h>
#include "atlasii.h"
#include "ipl.h"
#include "nand.h"

typedef void (*PFNLOCKCACHE)(unsigned dwAddr, unsigned dwSize, unsigned dwFlag);
unsigned	pfnLockCache;

#define CFG_SIGNATURE	0x86745312
extern void LockCache(unsigned addr, unsigned dwNumWay, unsigned flags);
extern void FlushICache(void);
extern void Show_LED(int led, int val);
extern void XipClkSwitch (unsigned dwPllCfg, unsigned dwClkRat);

void SDRPllSwitch(unsigned dwPllCfg, unsigned dwClkRat)
{
	volatile int i;
	//switch to xtal
	PWR_CLK_SWITCH=0x0;
	for(i=1;i<=100;i++);

	PWR_PLL1_CONFIG = dwPllCfg;
	PWR_CLK_RATIO = dwClkRat;
	for(i=1;i<=0x1000;i++);

	//switch to pll1
	PWR_CLK_SWITCH=0x01;
	for(i=1;i<=0x100;i++);
}

void PLL_SWITCH(unsigned dwPllCfg, unsigned dwClkRat)
{
	if ( ((dwClkRat >> 12) & 0xf) == ((dwClkRat >> 8) & 0xf) )
	{
		IOBG_ARB_CLKRATIO = 0x00; 
		RISCINT_WIDTH = 0x00; 
	}
	else	{ 
		IOBG_ARB_CLKRATIO = 0x01; 
		RISCINT_WIDTH = 0x10; 
	} 
	
	pfnLockCache = (unsigned ) LockCache;
	pfnLockCache |= 0xC0000000;
	FlushICache();
	((PFNLOCKCACHE)pfnLockCache)(((unsigned)SDRPllSwitch & ~0x1f), 1, 1);
	SDRPllSwitch (dwPllCfg, dwClkRat); 

	((PFNLOCKCACHE)pfnLockCache)(0, 0, 1);
}


int StartXipPllSwitch(unsigned dwClkSet)
{
	unsigned dwPllCfg, dwClkRatio;
	int i;
	switch (dwClkSet)
	{
		case SDR_276_184_92_46_CLOCK:   dwPllCfg = PLL1_552M; dwClkRatio=0xfffc632; break;
		case SDR_264_176_88_44_CLOCK:   dwPllCfg = PLL1_528M; dwClkRatio=0xfffc632; break;
		case SDR_252_168_84_42_CLOCK:   dwPllCfg = PLL1_504M; dwClkRatio=0xfffc632; break;
		case SDR_240_160_80_40_CLOCK:   dwPllCfg = PLL1_480M; dwClkRatio=0xfffc632; break;
		case SDR_228_152_76_38_CLOCK:   dwPllCfg = PLL1_456M; dwClkRatio=0xfffc632; break;
		case SDR_216_144_72_36_CLOCK:   dwPllCfg = PLL1_432M; dwClkRatio=0xfffc632; break;
		case SDR_276_184_92_92_CLOCK:   dwPllCfg = PLL1_552M; dwClkRatio=0xfff6632; break;
		case SDR_264_176_88_88_CLOCK:   dwPllCfg = PLL1_528M; dwClkRatio=0xfff6632; break;
		case SDR_252_168_84_84_CLOCK:   dwPllCfg = PLL1_504M; dwClkRatio=0xfff6632; break;
		case SDR_240_160_80_80_CLOCK:   dwPllCfg = PLL1_480M; dwClkRatio=0xfff6632; break;
		case SDR_228_152_76_76_CLOCK:   dwPllCfg = PLL1_456M; dwClkRatio=0xfff6632; break;
		case SDR_216_144_72_72_CLOCK:   dwPllCfg = PLL1_432M; dwClkRatio=0xfff6632; break;
		default:						
			return -1;
			break;
	}

	if(PWR_PLL1_CONFIG==dwPllCfg && ((PWR_CLK_RATIO & (dwClkRatio & 0xFFFF)) ==(dwClkRatio & 0xFFFF)))
		return -1;
#if 0	
	RESET_DECLARE(RESET_SR_SM_RST);
	RESET_CLEAR(RESET_SR_SM_RST);
#endif
	//debug flush
	while (!(UART_TXFIFO_STATUS & UART_TXFIFO_EMPTY)) ;

	 for (i = 0; i < 0x3000; ++i) {}

	(*(volatile unsigned int *)(_SMDF_MODULE_BASE+ 0x04)) 	= 0x1878; //SM_WAIT
	(*(volatile unsigned int *)(_SMDF_MODULE_BASE+ 0x28))   	|= 1;   // set to direct read mode
	(*(volatile unsigned int *)(_SMDF_MODULE_BASE+ 0xF00))  	= 3;    // set to IO read status
	(*(volatile unsigned int *)(_SMDF_MODULE_BASE+ 0xF04))     	= 0;
	(*(volatile unsigned int *)(_SMDF_MODULE_BASE+ 0xF10))   	= 1;    // must start FIFO

	PLL_SWITCH (dwPllCfg, dwClkRatio);
	return 0;
}

 int CheckClkCfg()
{
	unsigned char dwClkSet;
	unsigned char buf[PAGESIZE];
	if(nand_init()<0)
		return -1;
	nand_read_config((unsigned)buf);
	if(*(unsigned *)(buf)==CFG_SIGNATURE)
	{
		dwClkSet=buf[4];
		if(dwClkSet>=FIRST_CLOCK_SETTING && dwClkSet<=LAST_CLOCK_SETTING)
		{
			return (StartXipPllSwitch(dwClkSet));
		}
	}
	return -1;	
}
void board_init(void)
{
	int i=0;
	/*
	 * Set pin mux
	 */
       Show_LED(0, 5);
       
	ENABLE_CAMSM_PADH(); //make sure NAND take the pin
	ENABLE_CAMSM_PADL(); //make sure NAND take the pin
	PWR_CLK_EN |= PWRCLK_DMA_EN | PWRCLK_SM_EN | PWRCLK_IO_EN ;
	INT_RISC_MASK = 0;
	*(volatile unsigned char *)(EXT_PIO_BASE+0x1600) = 0x10; //SYS CTRL
	*(volatile unsigned char *)(EXT_PIO_BASE+0x1800) = 0x1; //RST CTRL
	*(volatile unsigned char *)(EXT_PIO_BASE+0x4400) = 0x22; //Enable USP0 P7
	*(volatile unsigned char *)(EXT_PIO_BASE+0x5000) = 0x0; //EPIO_PWR_CTRL
	// must keep the 0x02 (camera/nand)bit set t0 1, otherwise nand won't work.
	*(volatile unsigned char *)(EXT_PIO_BASE+0x5200) = 0x2; //EPIO_CAM_CTRL
	for(i = 0; i < 100; i++);
	//reset RTL8019
	// NBOOT code must reset net chip here, for when booting whole image from nand,
	// this mac chip will not work if it is not reset.
	*(volatile unsigned char *)(EXT_PIO_BASE+0x1800)  = 0x1;
	for(i = 0; i < 100; i++);
	*(volatile unsigned char *)(EXT_PIO_BASE+0x1800)  = 0x0;
	for(i = 0; i < 3000; i++);
}

int SelectClock()
{
	unsigned char dwClkSet;
	unsigned char buf[PAGESIZE];
	//bring out the menu:
	while(1){
		ser_putstr ((unsigned char *)"\n\t MEM_CPU_DSP_SYS_IO\n");
		ser_putstr((unsigned char *)"\ra) SDR_276_184_92_46\n");
		ser_putstr((unsigned char *)"\rb) SDR_264_176_88_44\n");
		ser_putstr((unsigned char *)"\rc) SDR_252_168_84_42\n");
		ser_putstr((unsigned char *)"\rd) SDR_240_160_80_40\n");
		ser_putstr((unsigned char *)"\re) SDR_228_152_76_38\n");
		ser_putstr((unsigned char *)"\rf) SDR_216_144_72_36\n");
		ser_putstr((unsigned char *)"\rg) SDR_276_184_92_92\n");
		ser_putstr((unsigned char *)"\rh) SDR_264_176_88_88\n");
		ser_putstr((unsigned char *)"\ri) SDR_252_168_84_84\n");
		ser_putstr((unsigned char *)"\rj) SDR_240_160_80_80\n");
		ser_putstr((unsigned char *)"\rk) SDR_228_152_76_76\n");
		ser_putstr((unsigned char *)"\rl) SDR_216_144_72_72\n");
		ser_putstr((unsigned char *)"\r1) return: \n");
		dwClkSet=ser_getchar();
		if(dwClkSet>=FIRST_CLOCK_SETTING && dwClkSet<=LAST_CLOCK_SETTING)
			break;
		if(dwClkSet=='1')
			return -1;
	} 
	if(nand_init()<0)
		return -1;
	nand_read_config((unsigned)buf);
	if(*(unsigned *)(buf)==CFG_SIGNATURE && dwClkSet==buf[4])
	{
		return -1;
	}
	//construct the buffer
	*(unsigned *)(buf)=CFG_SIGNATURE;
	buf[4]=dwClkSet;
	nand_write_config((unsigned)buf);
	
	return (StartXipPllSwitch(dwClkSet));
}