devio.h

Centrality Atlas II development software

/*
 * $QNXLicenseC: 
 * Copyright 2007,2008, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


#include <stdint.h>

//
// The spare area used for the NAND. It is 16 bytes in size. We combine
// two pages to give us a 1K cluster and a 32 byte effective spare area.
//
struct spare1 {
	uint32_t	sequence;			// Sequence number
	uint8_t		clusterhi;			// High order 8 bits of cluster
	uint8_t		status;				// Factory set - FF means good. Must be offset 6!!!
	uint16_t	fid;				// File id
	uint16_t	clusterlo;			// Low order 16 bits of logical cluster
	uint16_t	crcdatalo;			// Low order 16 bits of crc for readcluster()
	uint8_t		nclusters;			// Number of clusters
	uint8_t		erasesig;
	uint16_t	crctrans;			// Crc for readtrans()
};
#define ERASESIG	0xA0

struct spare2 {
	uint16_t	crcdatahi;			// High order 16 bits of crc
	uint8_t		ecc1[1][3];			// ECC for 1st 256 bytes
	uint8_t		status;				// Factory set - FF means good
	uint8_t		ecc234[3][3];		// ECC for 2nd,3rd,4th 256 bytes
	uint8_t		unused1;
};


// This struct is included in the chipio structure defined in the low level board driver
struct _chipio {
	unsigned	addrcycles;
	unsigned	lastcmd;
	unsigned	lastpage;
	unsigned	inspare;
 };

#ifndef CHIPIO
#define CHIPIO struct _chipio
#endif

//
// Nand device specific data structures
//
#define NANDCMD_SPAREREAD			0x50
#define NANDCMD_READ				0x00
#define NANDCMD_PROGRAM			0x80
#define NANDCMD_PROGRAMCONFIRM	0x10
#define NANDCMD_ERASE				0x60
#define NANDCMD_ERASECONFIRM		0xD0
#define NANDCMD_IDREAD			0x90
#define NANDCMD_STATUSREAD		0x70
#define NANDCMD_RESET				0xFF

#define DATASIZE					512
#define SPARESIZE					16
#define PAGESIZE					(DATASIZE + SPARESIZE)
#define PAGES2BLK					32
#define PAGES2CLUSTER				2


// These timeouts are very generous.
#define MAX_RESET_USEC				600		// 600us
#define MAX_READ_USEC				50      //  50us
#define MAX_POST_USEC				2000    //   2ms
#define MAX_ERASE_USEC				10000	//  10ms


// Prototype for entry into the filesystem
int  etfs_main(int argc, char *argv[]);

// Prototypes for chip interface
int  nand_init(struct etfs_devio *dev);
int  nand_wait_busy(CHIPIO *cio, uint32_t usec);
void nand_write_pageaddr(CHIPIO *cio, unsigned page, int addr_cycles);
void nand_write_blkaddr(CHIPIO *cio, unsigned blk, int addr_cycles);
void nand_write_cmd(CHIPIO *cio, int command);
int nand_write_data(CHIPIO *cio, uint8_t *databuffer, int data_cycles);
int nand_read_data(CHIPIO *cio, uint8_t *databuffer, int data_cycles);
int nand_read_flashid(CHIPIO *cio, uint8_t *id, int data_cycles);
int nand_read_status(CHIPIO *cio, uint8_t *databuffer);
int nand_read_page(CHIPIO *cio, unsigned page, uint8_t *databuffer, int data_cycles, int op);
int nand_write_page(CHIPIO *cio, unsigned page, uint8_t *databuffer, int data_cycles, int op);
int nand_erase_blk(CHIPIO *cio, unsigned blk);