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📄 atlasii.h

📁 Centrality Atlas II development software
💻 H
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/* * $QNXLicenseC:  * Copyright 2007,2008, QNX Software Systems.   *   * Licensed under the Apache License, Version 2.0 (the "License"). You   * may not reproduce, modify or distribute this software except in   * compliance with the License. You may obtain a copy of the License   * at: http://www.apache.org/licenses/LICENSE-2.0   *   * Unless required by applicable law or agreed to in writing, software   * distributed under the License is distributed on an "AS IS" basis,   * WITHOUT WARRANTIES OF ANY KIND, either express or implied.  *  * This file may contain contributions from others, either as   * contributors under the License or as licensors under other terms.    * Please review this entire file for other proprietary rights or license   * notices, as well as the QNX Development Suite License Guide at   * http://licensing.qnx.com/license-guide/ for other information.  * $  */#ifndef __ATLASII_H#define __ATLASII_H/* *  Definitions for ATLASII chip */struct	atlasii_card;#define  HW_CONTEXT_T struct atlasii_card#define  PCM_SUBCHN_CONTEXT_T ado_pcm_subchn_t#include <audio_driver.h>#include <mixer/ac97_dll.h>#define NANOSPIN_TIME					1000#define AC97_INITDEV_TO					1000#define ATLASII_AC97_BASE				0x80060000#define ATLASII_DMA_BASE				0xB0000000#define ATLASII_DMA_INT_NUM				100#define PWRCLK_DMA_EN					(1 << 2)    //  DMA Controller clock enable#define PWRCLK_CODEC_EN     			(1 << 8)    //  CODEC clock enable#define PWRCLK_IO_EN        			(1 << 21)   //  I/O clock enabletypedef volatile uint32_t	vuint32_t;typedef struct {	vuint32_t				rSHARE;	vuint32_t				rUDA_CTRL;	vuint32_t				__filler0[5];	vuint32_t				rCTRL;	vuint32_t				rCMD;	vuint32_t				rRTAGH;	vuint32_t				rSTATUS;	vuint32_t				rREG_OK;	vuint32_t				rSLOT12_DATA;	vuint32_t				rTXSLOT_EN;	vuint32_t				rRXSLOT_EN;	vuint32_t				__filler1[721];	vuint32_t				rTX_AUX_DMA_IO_CTRL;	vuint32_t				r__filler2;	vuint32_t				rTX_AUX_FIFO_CTRL;	vuint32_t				rTX_AUX_FIFO_LEVEL_CHK;	vuint32_t				rTX_AUX_FIFO_OP;	vuint32_t				rTX_AUX_FIFO_STS;		vuint32_t				rTX_AUX_FIFO_INT_EN;	vuint32_t				__filler3[9];	vuint32_t				rRX_AUX_DMA_IO_CTRL;	vuint32_t				r__filler4;	vuint32_t				rRX_AUX_FIFO_CTRL;	vuint32_t				rRX_AUX_FIFO_LEVEL_CHK;	vuint32_t				rRX_AUX_FIFO_OP;	vuint32_t				rRX_AUX_FIFO_STS;		vuint32_t				rRX_AUX_FIFO_INT_EN;	vuint32_t				__filler5[233];	vuint32_t				rTX_DMA_IO_CTRL;	vuint32_t				r__filler6;	vuint32_t				rTX_FIFO_CTRL;	vuint32_t				rTX_FIFO_LEVEL_CHK;	vuint32_t				rTX_FIFO_OP;	vuint32_t				rTX_FIFO_STS;		vuint32_t				rTX_FIFO_INT_EN;	vuint32_t				__filler7[9];	vuint32_t				rRX_DMA_IO_CTRL;	vuint32_t				r__filler8;	vuint32_t				rRX_FIFO_CTRL;	vuint32_t				rRX_FIFO_LEVEL_CHK;	vuint32_t				rRX_FIFO_OP;	vuint32_t				rRX_FIFO_STS;		vuint32_t				rRX_FIFO_INT_EN;}ac97_t;typedef struct {	vuint32_t	rADDR;									// 00	vuint32_t	rXLEN;									// 04	vuint32_t	rYLEN;									// 08	vuint32_t	rCTRL;									// 0C} dma_reg_t;/*DMA common reg offset*/#define ATLASII_DMA_COMMON_OFF				0x100typedef struct {	vuint32_t	rWIDTH0;								// 00	vuint32_t	rWIDTH1;								// 04	vuint32_t	rWIDTH2;								// 08	vuint32_t	rWIDTH3;								// 0C	vuint32_t	rCH_VALID;								// 10	vuint32_t	rCH_INT;								// 14	vuint32_t	rINT_EN;								// 18	vuint32_t	rCH_DSP_CTRL;							// 14	vuint32_t	rCH_LOOP_CTRL;							// 18} dma_common_reg_t;typedef struct stream {	uint32_t			dma_ch;	uint32_t            dma_irq;	ado_pcm_cap_t       pcm_caps;	ado_pcm_hw_t        pcm_funcs;	dma_reg_t           *dma;	ado_pcm_subchn_t    *pcm_subchn;	ado_pcm_config_t    *pcm_config;	uint32_t            pcm_cur_frag;}stream_t;struct atlasii_card {	uint32_t						atlasii_base;	uint32_t						dma_base;	uint32_t						ctrl_irq;		ado_mutex_t						hw_lock;	ado_pcm_t 						*pcm1;	ado_mixer_t						*mixer;	ado_mixer_dll_callbacks_ac97_t	mixer_cb;	ac97_t							*ac97_ctrl;	dma_common_reg_t				*common_dma;	stream_t						play_strm;	stream_t						cap_strm;};typedef struct atlasii_card atlasii_t;#endif	

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