main.c

Centrality Atlas II development software

/*
 * $QNXLicenseC: 
 * Copyright 2007,2008, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */






#include "startup.h"
#include "atlasii.h"
extern struct callout_rtn	poll_key_atlasii;
extern struct callout_rtn	display_char_atlasii;
extern struct callout_rtn	break_detect_atlasii;
extern struct callout_rtn	reboot_atlasii;
extern void init_atlasii(unsigned channel, const char *init, const char *defaults);
extern void put_atlasii(int c);


const struct callout_slot callouts[] = {
	{ CALLOUT_SLOT( reboot, _atlasii ) },
};

const struct debug_device debug_devices[] = {
	{ 	"atlasii",
		{	"0x80000000.115200.0.16",	
		},
		init_atlasii,
		put_atlasii,
		{	&display_char_atlasii,
			&poll_key_atlasii,
			&break_detect_atlasii,
		}
	},
};


/*
 * We assume the DPLL is in lock mode
 */
 //op=0, CPU CLOCK 
 //op=1, SYSCLOCK
 //op=2, IOCLCK
 //op=3, DSP_CLOCK

unsigned long atlasii_clock(int OP) {
#define FREQ_IN			12000000

	unsigned int dwPll1Clk; 
	unsigned int dwClk;
	unsigned int dwSysClkSW, dwRat=1;
	unsigned int dwFd, dwId, dwOd;
	unsigned int bBp;

	dwSysClkSW = PWR_CLK_SWITCH & 0x3;
		
	dwClk = PWR_PLL1_CONFIG;
	bBp = (dwClk >> 11) & 1;
	if (bBp)
	{
		dwPll1Clk = FREQ_IN;
	}
	else
	{
		dwFd = dwClk & 0x3f;
		dwId = (dwClk >> 6) & 0xf;
		dwOd = (dwClk >> 10) & 1;

		dwPll1Clk = FREQ_IN * ((3 - (dwOd + 1)) * (dwFd + 2)) / (dwId + 1);
	}


	switch (dwSysClkSW)
	{
	case 0:
		dwClk = FREQ_IN;
		break;
	case 1:
		dwClk = dwPll1Clk;
		break;
	default:
		break;
	}
	switch(OP)
	{
	case 0: //cpu clock
		dwRat = (PWR_CLK_RATIO ) & 0xf;
		break;
	case 1: //sysclock
		dwRat = (PWR_CLK_RATIO >>8 ) & 0xf;
		break;
	case 2: //ioclock
		dwRat = (PWR_CLK_RATIO>>12 ) & 0xf;
		break;
	case 3: //dsp clock
		dwRat = (PWR_CLK_RATIO >>4) & 0xf;
		break;
	default:
		kprintf("Unkbown type of clock\n");
		dwRat=1;
		break;	
	}
	
	if ((dwRat > 8) && (dwRat & 0x3))
	{
		dwRat = (dwRat & ~0x3) + 4;
	}
	else if ((dwRat > 4) && (dwRat & 0x1))
	{
		dwRat = (dwRat & ~0x1) + 2;
	}

	if(OP==3 && dwRat==12)  //usb
		dwRat=16;
	
	if(dwRat==0)
	{
		kprintf("Unexpected Clock Ratio 0, should be at leasrt 1\n");
		return 0;
	}
		
	return dwClk / dwRat;
}


static void set_pci_clk_freq()
{
	int i;
	uint32_t regval;
	//Enable PCI and USB clock
	PWR_CLK_EN |=(1<<22)|(1 << 5);
	RESET_DECLARE(RESET_SR_IOM_RST);
	RESET_CLEAR(RESET_SR_IOM_RST);
	for(i=0; i<1000; i++) ;
	// set PLL2 to 192 MHz
	PWR_PLL2_CONFIG = 0x4220;
	for(i=0;i<1000;i++);

	// set usb clock ratio to pll2:usb_clk=4:1
	regval = PWR_CLK_RATIO;
	regval &= ~0xf0000;
	regval |= 0x40000;
	PWR_CLK_RATIO =regval;
	for(i=0; i<1000; i++) ;

	// set USB clock source to PLL2
	regval = PWR_CLK_SWITCH;
	regval &= ~0x0c;
	regval |= 0x08;
	PWR_CLK_SWITCH = regval;
	for(i=0; i<1000; i++) ;
}
/*
 * main()
 *	Startup program executing out of RAM
 *
 * 1. It gathers information about the system and places it in a structure
 *    called the system page. The kernel references this structure to
 *    determine everything it needs to know about the system. This structure
 *    is also available to user programs (read only if protection is on)
 *    via _syspage->.
 *
 * 2. It (optionally) turns on the MMU and starts the next program
 *    in the image file system.
 */
int
main(int argc, char **argv, char **envv)
{
	int			opt;
	/* UNCOMMENT for CAN MINI-DRIVER OR SERIAL MINI-DRIVER */
	//paddr_t 	mdrvr_addr;

	add_callout_array(callouts, sizeof(callouts));

	while ((opt = getopt(argc, argv, COMMON_OPTIONS_STRING)) != -1) {
		handle_common_option(opt);
	}

	/*
	 * Initialise debugging output
	 */
	select_debug(debug_devices, sizeof(debug_devices));

	/*
	 * Collect information on all free RAM in the system
	 */
	init_raminfo();

	/*
	 * set CPU frequency
	 */
	cpu_freq = atlasii_clock(0); 
	kprintf("\ncpu_clock=%d, dsp_clock=%d, sys_clck=%d, io_clock=%d\n", cpu_freq, atlasii_clock(3), atlasii_clock(1), atlasii_clock(2));

	set_pci_clk_freq();

	/* 
	 * Remove RAM used by modules in the image
	 */
	//alloc_ram(shdr->ram_paddr, shdr->ram_size, 1);
	if (shdr->flags1 & STARTUP_HDR_FLAGS1_VIRTUAL)
		init_mmu();
	init_intrinfo();
	init_qtime();
	init_cacheattr();
	init_cpuinfo();
	init_hwinfo();
	add_typed_string(_CS_MACHINE, "Centrality Communication Atlas-II EVB");

	/*
	 * Load bootstrap executables in the image file system and Initialise
	 * various syspage pointers. This must be the _last_ initialisation done
	 * before transferring control to the next program.
	 */
	init_system_private();

	/*
	 * This is handy for debugging a new version of the startup program.
	 * Commenting this line out will save a great deal of code.
	 */
	print_syspage();


	return 0;
}