atlasii.h

Centrality Atlas II development software

#define INT_FIQ_PENDING                         (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0008))
#define INT_DSP0_PENDING                        (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x000c))
#define INT_RISC_MASK                           (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0010))
#define INT_DSP_MASK                            (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0014))
#define INT_RISC_LEVEL                          (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0018))
#define INT_DSP_ACCEN                           (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x001c))
#define INT_CHIP_ID                             (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0020))
#define INT_DSP_LEVEL                           (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0024))
#define INT_DSP1_PENDING                        (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0028))
#define INT_RISC_MASK_EXT                  (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x002C))
#define INT_DSP_MASK_EXT                   (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0030))
#define INT_PENDING_EXT                         (*(volatile unsigned int *)(_INT_MODULE_BASE + 0x0034))

/***************************************************************************************\
| Powerdonw and Clocks and PLL registers
\***************************************************************************************/
#define PWR_CTRL                               (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0000))
#define PWR_CONFIG                             (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0004))
#define PWR_WAKEUP_EN                          (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0008))
#define PWR_SLEEP_STATUS                       (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x000c))
#define PWR_SCRATCH_PAD                        (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0010))
#define PWR_OSC_STATUS                         (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x001c))
#define PWR_CLK_SWITCH                         (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0020))
#define PWR_PLL1_CONFIG                        (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0028))
#define PWR_PLL2_CONFIG                        (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x002c))
#define PWR_CLK_EN                             (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0030))
#define PWR_WAIT_TIME                          (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0034))
#define PWR_STOP_LEVEL                         (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0038))
#define PWR_PIN_RELEASE                        (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x003c))
#define PWR_CLK_RATIO                          (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0040))
#define PWR_XIN_RATIO                          (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0044))
#define PWR_PAD_CTRL                           (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0048))
#define PWR_DELAY_CTRL0                        (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x004c))
#define PWR_DELAY_CTRL1                        (*(volatile unsigned int *)(_POWER_MODULE_BASE + 0x0050))


#define PLL1_600M                              0x00000017
#define PLL1_576M                              0x00000016
#define PLL1_552M                              0x00000015
#define PLL1_528M                              0x00000014
#define PLL1_504M                              0x00000013
#define PLL1_480M                              0x00000426
#define PLL1_456M                              0x00000424
#define PLL1_432M                              0x00000422
#define PLL1_408M                              0x00000420
#define PLL1_396M                              0x0000041F
#define PLL1_300M                              0x00000417
#define PLL1_288M                              0x00000416
#define PLL1_276M                              0x00000415
#define PLL1_264M                              0x00000414
#define PLL1_252M                              0x00000413

#define PLL2_192M                              0x00004220
#define PLL2_96M                               0x00006220


// DDR
#define DDR_204_204_204_102_CLOCK               'a'
#define DDR_300_150_150_75_CLOCK                'b'
// SDR
// CPU:DSP:SYS:IO=4:2:2:1
#define SDR_252_126_126_63_CLOCK                'c'
#define SDR_240_120_120_60_CLOCK                'd'
// CPU:DSP:SYS:IO=6:4:2:1
#define SDR_300_200_100_50_CLOCK                'e'
#define SDR_288_192_96_48_CLOCK                 'f'
#define SDR_276_184_92_46_CLOCK                 'g'
#define SDR_264_176_88_44_CLOCK                 'h'
#define SDR_252_168_84_42_CLOCK                 'i'
#define SDR_240_160_80_40_CLOCK                 'j'
#define SDR_228_152_76_38_CLOCK                 'k'
#define SDR_216_144_72_36_CLOCK                 'l'
// CPU:DSP:SYS:IO=3:2:1:1
#define SDR_300_200_100_100_CLOCK               'm'
#define SDR_288_192_96_96_CLOCK                 'n'
#define SDR_276_184_92_92_CLOCK                 'o'
#define SDR_264_176_88_88_CLOCK                 'p'
#define SDR_252_168_84_84_CLOCK                 'q'
#define SDR_240_160_80_80_CLOCK                 'r'
#define SDR_228_152_76_76_CLOCK                 's'
#define SDR_216_144_72_72_CLOCK                 't'
// SOCKET BOARD CLOCK SET
#define SDR_48_32_16_8_CLOCK                    'u'
#define SDR_48_32_16_16_CLOCK                   'v'
#define SDR_48_24_24_12_CLOCK                   'w'
#define SDR_48_24_24_24_CLOCK                   'x'

#define FIRST_CLOCK_SETTING                     DDR_204_204_204_102_CLOCK
#define LAST_CLOCK_SETTING                      SDR_216_144_72_72_CLOCK

/***************************************************************************************\
| Resource Sharing registers
\***************************************************************************************/
#define RSC_PIN_MUX                             (*(volatile unsigned int *)(_RSC_MODULE_BASE + 0x0004))
#define RSC_DMA_MUX                             (*(volatile unsigned int *)(_RSC_MODULE_BASE + 0x0008))

/***************************************************************************************\
| Real-time clock registers
\***************************************************************************************/
#define RTC_COUNTER                             (*(volatile unsigned int *)_RTC_MODULE_BASE)
#define RTC_ALARM                               (*(volatile unsigned int *)(_RTC_MODULE_BASE + 0x0004))
#define RTC_STATUS                              (*(volatile unsigned int *)(_RTC_MODULE_BASE + 0x0008))
#define RTC_DIV                                 (*(volatile unsigned int *)(_RTC_MODULE_BASE + 0x000c))

/***************************************************************************************\
| OS timer registers
\***************************************************************************************/
#define TIMER_COUNTER_LO                        (*(volatile unsigned int *)_OST_MODULE_BASE)
#define TIMER_COUNTER_HI                        (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0004))
#define TIMER_MATCH_0                           (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0008))
#define TIMER_MATCH_1                           (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x000c))
#define TIMER_MATCH_2                           (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0010))
#define TIMER_MATCH_3                           (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0014))
#define TIMER_MATCH_4                           (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0018))
#define TIMER_MATCH_5                           (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x001c))
#define TIMER_STATUS                            (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0020))
#define TIMER_INT_EN                            (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0024))
#define TIMER_WATCHDOG_EN                       (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0028))
#define TIMER_DIV                               (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x002c))
#define TIMER_LATCH                             (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0030))
#define TIMER_LATCHED_LO                        (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0034))
#define TIMER_LATCHED_HI                        (*(volatile unsigned int *)(_OST_MODULE_BASE + 0x0038))

/***************************************************************************************\
| Reset controller registers
\***************************************************************************************/
#define RESET_SR                                (*(volatile unsigned int *)_RESET_MODULE_BASE)
#define RESET_STATUS                            (*(volatile unsigned int *)(_RESET_MODULE_BASE + 0x0004))

/***************************************************************************************\
| General-purposed I/O registers
\***************************************************************************************/

#define GPIO0_CTRL0                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0000))
#define GPIO0_CTRL1                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0004))
#define GPIO0_CTRL2                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0008))
#define GPIO0_CTRL3                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x000c))
#define GPIO0_CTRL4                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0010))
#define GPIO0_CTRL5                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0014))
#define GPIO0_CTRL6                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0018))
#define GPIO0_CTRL7                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x001c))
#define GPIO0_CTRL8                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0020))
#define GPIO0_CTRL9                               (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0024))
#define GPIO0_CTRL10                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0028))
#define GPIO0_CTRL11                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x002c))
#define GPIO0_CTRL12                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0030))
#define GPIO0_CTRL13                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0034))
#define GPIO0_CTRL14                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0038))
#define GPIO0_CTRL15                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x003c))
#define GPIO0_CTRL16                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0040))
#define GPIO0_CTRL17                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0044))
#define GPIO0_CTRL18                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0048))
#define GPIO0_CTRL19                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x004c))
#define GPIO0_CTRL20                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0050))
#define GPIO0_CTRL21                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0054))
#define GPIO0_CTRL22                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x0058))
#define GPIO0_CTRL23                              (*(volatile unsigned int *)(_GPIO_MODULE_BASE + 0x005c))