callout_reboot_atlasii.s

Centrality Atlas II development software

#  
# Copyright 2007, 2008, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# #
/*
 * Centrality Atlas-II system reboot
 */

#include "callout.ah"
#include "atlasii.h"

#define CLK_RATIO_val		0x2111
#define WAIT_REG_val		0x1878

/*
 * -----------------------------------------------------------------------
 * Routine to patch callout code
 *
 * On entry:
 *	r0 - physical address of syspage
 *	r1 - virtual  address of syspage
 *	r2 - offset from start of syspage to start of the callout routine
 *	r3 - offset from start of syspage to read/write data used by callout
 * -----------------------------------------------------------------------
 */

patch_reboot:
	stmdb	sp!,{r4,lr}
	add		r4, r0, r2					// address of callout routine

	/*
	 * Map reset control registers
	 */
	mov		r0, #0x08	// size of reset control registers
	ldr		r1, Lpaddr
	bl		callout_io_map

	/*
	 * Patch the callout routine
	 */
	CALLOUT_PATCH	r4, r0, r1, r2, ip


       /*
         * Patch callout routine with SmartMedia register address
         */
 	mov		r0, #0xF20	// size of SmartMedia registers
	ldr		r1, Lpaddr1
	bl		callout_io_map
       CALLOUT_PATCH        r4, r0, r1, r2, ip

       /*
         * Patch callout routine with Power Module register address
         */
 	mov		r0, #0x60	// size of Power Module registers
	ldr		r1, Lpaddr2
	bl		callout_io_map
       CALLOUT_PATCH        r4, r0, r1, r2, ip

	ldmia	sp!,{r4,pc}

Lpaddr:	.word	_RESET_MODULE_BASE
Lpaddr1:	.word	_SMDF_MODULE_BASE
Lpaddr2:	.word	_POWER_MODULE_BASE

CALLOUT_START(reboot_atlasii, 0, patch_reboot)
    /*
     * Get the base address of Clock, Reset, and Power Mode Control registers (patched)
     */

    mov     ip,   #0x000000ff    			   // Reset Module register offset
    orr     ip, ip, #0x0000ff00
    orr     ip, ip, #0x00ff0000
    orr     ip, ip, #0xff000000

    mov              r0,     #0x000000ff                // SmartMedia register offset
    orr                r0, r0, #0x0000ff00
    orr                r0, r0, #0x00ff0000
    orr                r0, r0, #0xff000000

    mov              r1,     #0x000000ff                // Power Module register offset
    orr                r1, r1, #0x0000ff00
    orr                r1, r1, #0x00ff0000
    orr                r1, r1, #0xff000000


   ldr			r2, [r1, #0x20]  //POWER_CLK_SWITCH
   bic		r2, r2, #3
   str			r2, [r1, #0x20]

   //wait for some time
   mov		r3, #0x3000
wait0: 
   sub		r3, r3, #1
   cmp		r3, #0
   bne		wait0

 
   ldr     r2,  =CLK_RATIO_val
   str			r2, [r1, #0x40]  //POWER_CLK_RATIO
   //wait for some time
   mov		r3, #0x3000
wait1: 
   sub		r3, r3, #1
   cmp		r3, #0
   bne		wait1

   ldr     r2,  =WAIT_REG_val
   str			r2, [r0, #0x04]  //SMDF_WAIT_REG

   mov		r2, #0xf
   str			r2, [r0, #0x24]  //SMDF_INT_STATUS_REG

   ldr			r2, [r0, #0x28]  //set direct mode
   orr		r2, r2, #1
   str			r2, [r0, #0x28]

   mov		r2, #0x3
   str			r2, [r0, #0xF00]  //SMDF_DMA_IO_CTRL_REG

   mov		r2, #0
   str			r2, [r0, #0xF04]  //SMDF_DMA_IO_LEN_REG


   mov		r2, #1    //must start FIFO
   str			r2, [r0, #0xF10]  //SMDF_FIFO_OP_REG

    mov		r2, #1
    ldr		r1, [ip]
    orr		r1, r1, r2, lsl #31
    str		r1, [ip]
0:      b                0b

CALLOUT_END(reboot_atlasii)