hw_seratlasii.c

Centrality Atlas II development software

/*
 * $QNXLicenseC: 
 * Copyright 2007,2008, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */




#include "startup.h"
#include "atlasii.h"

/*
 * Drive ATLAS-II serial channel (similar to 8250)
 */
extern unsigned long atlasii_clock(int OP);
void put_atlasii(int c) {
	while (UART_TXFIFO_STATUS & UART_TXFIFO_FULL) {}
	UART_TXFIFO_DATA = c;
}

static void
parse_line(unsigned channel, const char *line, unsigned long *baud, unsigned long *clk, unsigned long *div) {
	
    if(*line != '.' && *line != '\0') {
		dbg_device[channel].base = strtoul(line, (char **)&line, 16);
		if(*line == '^') dbg_device[channel].shift = strtoul(line+1, (char **)&line, 0);
	}
    if(*line == '.') ++line;
    if(*line != '.' && *line != '\0') *baud = strtoul(line, (char **)&line, 0);
    if(*line == '.') ++line;
    if(*line != '.' && *line != '\0') *clk = strtoul(line, (char **)&line, 0);
    if(*line == '.') ++line;
    if(*line != '.' && *line != '\0') *div = strtoul(line, (char **)&line, 0);
}

void
init_atlasii(unsigned channel, const char *init, const char *defaults) {
	unsigned long 	baud;
	unsigned long	div;
	unsigned long	clk;
	paddr_t			base;
	int i;

	baud = 0;
	parse_line(channel, defaults, &baud, &clk, &div);
	parse_line(channel, init, &baud, &clk, &div);

	base = dbg_device[channel].base;
	if(clk==0)
		clk=atlasii_clock(2); //get io-clock
	baud = (clk*2/(div*baud))/2-1;
	// for safety reason, reset the uart block
	PWR_CLOCK_ENABLE(PWRCLK_SP0_EN);
	RESET_DECLARE(RESET_SR_SP0_RST);
	for(i=0; i<10; i++);
	RESET_CLEAR(RESET_SR_SP0_RST);
	for(i=0; i<10; i++);
	ENABLE_USP0_DATA_PAD();// release pin to USP0 txd and rxd
	ENABLE_USP0_CTRL_PAD();// release pin to USP0 flow control

	UART_DIVISOR = baud |((div-1)<<16);
	UART_LINE_CTRL = 3;
	UART_TX_DMA_IO_CTRL = UART_TX_IO_MODE;
	UART_RX_DMA_IO_CTRL = UART_RX_IO_MODE;
	UART_TX_DMA_IO_LEN = 0;
	UART_RX_DMA_IO_LEN = 0;
	UART_TXFIFO_CTRL = 0x08 ;
	UART_RXFIFO_CTRL = 0x18 ;
	UART_TXFIFO_LEVEL_CHK = 0x06 | (0x04 << 10) | (0x02 << 20);
	UART_RXFIFO_LEVEL_CHK = 0x02 | (0x04 << 10) | (0x06 << 20);
	UART_TXRX_ENA_REG = UART_RX_EN | UART_TX_EN;
	// Fifo Reset
	UART_TXFIFO_OP = UART_TXFIFO_RESET;
	UART_RXFIFO_OP = UART_RXFIFO_RESET;
	// Fifo Start
	UART_TXFIFO_OP = UART_TXFIFO_START;
	UART_RXFIFO_OP = UART_RXFIFO_START;
	// clear all pending uart interrupts
	UART_INT_STATUS = UART_INT_MASK_ALL;
}