sa1100.h

Centrality Atlas II development software

/*
 * $QNXLicenseC:
 * Copyright 2008, QNX Software Systems. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License"). You 
 * may not reproduce, modify or distribute this software except in 
 * compliance with the License. You may obtain a copy of the License 
 * at: http://www.apache.org/licenses/LICENSE-2.0 
 * 
 * Unless required by applicable law or agreed to in writing, software 
 * distributed under the License is distributed on an "AS IS" basis, 
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as 
 * contributors under the License or as licensors under other terms.  
 * Please review this entire file for other proprietary rights or license 
 * notices, as well as the QNX Development Suite License Guide at 
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */




/*
 * SA-1100 processor
 *

 *
 */

#ifndef	__ARM_SA1100_H_INCLUDED
#define	__ARM_SA1100_H_INCLUDED

/*
 * -------------------------------------------------------------------------
 * GPIO controller
 * -------------------------------------------------------------------------
 */
#define	SA1100_GPIO_BASE	0x90040000		/* base physical address */
#define	SA1100_GPIO_SIZE	0x00000020

/*
 * Register offsets from SA1100_GPIO_BASE
 */
#define	SA1100_GPLR			0x00			/* pin level register */
#define	SA1100_GPDR			0x04			/* pin direction register */
#define	SA1100_GPSR			0x08			/* pin output set register */
#define	SA1100_GPCR			0x0c			/* pin output clear register */
#define	SA1100_GRER			0x10			/* rising edge detect register */
#define	SA1100_GFER			0x14			/* falling edge detect register */
#define	SA1100_GEDR			0x18			/* edge detect status register */
#define	SA1100_GAFR			0x1c			/* alternate function register */

/*
 * GPIO pins
 */
#define	SA1100_GPIO_0		(1 <<  0)		/* GPIO Pin 0 */
#define	SA1100_GPIO_1		(1 <<  1)		/* GPIO Pin 1 */
#define	SA1100_GPIO_2		(1 <<  2)		/* GPIO Pin 2 */
#define	SA1100_GPIO_3		(1 <<  3)		/* GPIO Pin 3 */
#define	SA1100_GPIO_4		(1 <<  4)		/* GPIO Pin 4 */
#define	SA1100_GPIO_5		(1 <<  5)		/* GPIO Pin 5 */
#define	SA1100_GPIO_6		(1 <<  6)		/* GPIO Pin 6 */
#define	SA1100_GPIO_7		(1 <<  7)		/* GPIO Pin 7 */
#define	SA1100_GPIO_8		(1 <<  8)		/* GPIO Pin 8 */
#define	SA1100_GPIO_9		(1 <<  9)		/* GPIO Pin 9 */
#define	SA1100_GPIO_10		(1 << 10)		/* GPIO Pin 10 */
#define	SA1100_GPIO_11		(1 << 11)		/* GPIO Pin 11 */
#define	SA1100_GPIO_12		(1 << 12)		/* GPIO Pin 12 */
#define	SA1100_GPIO_13		(1 << 13)		/* GPIO Pin 13 */
#define	SA1100_GPIO_14		(1 << 14)		/* GPIO Pin 14 */
#define	SA1100_GPIO_15		(1 << 15)		/* GPIO Pin 15 */
#define	SA1100_GPIO_16		(1 << 16)		/* GPIO Pin 16 */
#define	SA1100_GPIO_17		(1 << 17)		/* GPIO Pin 17 */
#define	SA1100_GPIO_18		(1 << 18)		/* GPIO Pin 18 */
#define	SA1100_GPIO_19		(1 << 19)		/* GPIO Pin 19 */
#define	SA1100_GPIO_20		(1 << 20)		/* GPIO Pin 20 */
#define	SA1100_GPIO_21		(1 << 21)		/* GPIO Pin 21 */
#define	SA1100_GPIO_22		(1 << 22)		/* GPIO Pin 22 */
#define	SA1100_GPIO_23		(1 << 23)		/* GPIO Pin 23 */
#define	SA1100_GPIO_24		(1 << 24)		/* GPIO Pin 24 */
#define	SA1100_GPIO_25		(1 << 25)		/* GPIO Pin 25 */
#define	SA1100_GPIO_26		(1 << 26)		/* GPIO Pin 26 */
#define	SA1100_GPIO_27		(1 << 27)		/* GPIO Pin 27 */

/*
 * -------------------------------------------------------------------------
 * Peripheral Pin controller
 * -------------------------------------------------------------------------
 */

#define	SA1100_PPC_BASE		0x90060000		/* base physical address */
#define	SA1100_PPC_SIZE		0x00000014

/*
 * Register offsets from SA1100_PPC_BASE
 */
#define	SA1100_PPDR			0x00			/* pin direction register */
#define	SA1100_PPSR			0x04			/* pin status register */
#define	SA1100_PPAR			0x08			/* pin assignment register */
#define	SA1100_PSDR			0x0c			/* sleep mode direction register */
#define	SA1100_PPFR			0x10			/* pin flag register */

/*
 * PPDR/PPSR/PSDR bits
 *
 * For PPDR:
 *	- setting a bit to 0 configures pin for input
 *	- setting a bit to 1 configures pin as output
 *
 * For PPSR:
 *	- reads return current state of the peripheral pin
 *	- writes set/clear pins configured as outputs
 *
 * For PSDR:
 *	- setting a bit to 0 configures pin as output during sleep (driven low)
 *	- setting a bit to 1 configures pin as input during sleep
 */
#define	SA1100_PPC_LDD0		(1 <<  0)		/* LCD data pin 0 */
#define	SA1100_PPC_LDD1		(1 <<  1)		/* LCD data pin 1 */
#define	SA1100_PPC_LDD2		(1 <<  2)		/* LCD data pin 2 */
#define	SA1100_PPC_LDD3		(1 <<  3)		/* LCD data pin 3 */
#define	SA1100_PPC_LDD4		(1 <<  4)		/* LCD data pin 4 */
#define	SA1100_PPC_LDD5		(1 <<  5)		/* LCD data pin 5 */
#define	SA1100_PPC_LDD6		(1 <<  6)		/* LCD data pin 6 */
#define	SA1100_PPC_LDD7		(1 <<  7)		/* LCD data pin 7 */
#define	SA1100_PPC_L_PCLK	(1 <<  8)		/* LCD pixel clock pin */
#define	SA1100_PPC_L_LCLK	(1 <<  9)		/* LCD line clock pin */
#define	SA1100_PPC_L_FCLK	(1 << 10)		/* LCD frame clock pin */
#define	SA1100_PPC_L_BIAS	(1 << 11)		/* LCD AC bias pin */
#define	SA1100_PPC_TXD1		(1 << 12)		/* Serial Port 1 Tx pin */
#define	SA1100_PPC_RXD1		(1 << 13)		/* Serial Port 1 Rx pin */
#define	SA1100_PPC_TXD2		(1 << 14)		/* Serial Port 2 Tx pin	*/
#define	SA1100_PPC_RXD2		(1 << 15)		/* Serial Port 2 Rx pin	*/
#define	SA1100_PPC_TXD3		(1 << 16)		/* Serial Port 3 Tx pin */
#define	SA1100_PPC_RXD3		(1 << 17)		/* Serial Port 3 Rx pin */
#define	SA1100_PPC_TXD4		(1 << 18)		/* Serial Port 4 Tx pin */
#define	SA1100_PPC_RXD4		(1 << 19)		/* Serial Port 4 Rx pin */
#define	SA1100_PPC_SCLK		(1 << 20)		/* Serial Port 4 serial clock pin */
#define	SA1100_PPC_SFRM		(1 << 21)		/* Serial Port 4 serial frame pin */

/*
 * PPAR register bits
 */
#define	SA1100_PPAR_UPR		(1 << 12)		/* Reassign Serial Port 1 UART pins */
#define	SA1100_PPAR_SPR		(1 << 18)		/* Reassign Serial Port 4 SSP pins */

/*
 * PPFR register bits
 */
#define	SA1100_PPFR_LCD		(1 <<  0)		/* LCD controller flag */
#define	SA1100_PPFR_SP1_TX	(1 << 12)		/* Serial Port 1 Tx flag */
#define	SA1100_PPFR_SP1_RX	(1 << 13)		/* Serial Port 1 Rx flag */
#define	SA1100_PPFR_SP2_TX	(1 << 14)		/* Serial Port 2 Tx flag */
#define	SA1100_PPFR_SP2_RX	(1 << 15)		/* Serial Port 2 Rx flag */
#define	SA1100_PPFR_SP3_TX	(1 << 16)		/* Serial Port 3 Tx flag */
#define	SA1100_PPFR_SP3_RX	(1 << 17)		/* Serial Port 3 Rx flag */
#define	SA1100_PPFR_SP4		(1 << 18)		/* Serial Port 4 flag */

/*
 * -------------------------------------------------------------------------
 * Interrupt controller
 * -------------------------------------------------------------------------
 */

#define	SA1100_INTR_BASE	0x90050000	/* base physical address */
#define	SA1100_INTR_SIZE	0x00000024

/*
 * Register offsets from SA1100_INTR_BASE
 */
#define	SA1100_ICIP			0x00		/* IRQ pending register */
#define	SA1100_ICMR			0x04		/* mask register */
#define	SA1100_ICLR			0x08		/* level register */
#define	SA1100_ICCR			0x0c		/* control register */
#define	SA1100_ICFP			0x10		/* FIQ pending register */
#define	SA1100_ICPR			0x20		/* pending registers */

/*
 * ICCR bits
 */
#define	SA1100_ICCR_DIM		0x000000001	/* disable idle mask */

/*
 * Interrupt vectors
 */
#define	SA1100_INTR_GPIO_0		0		/* GPIO edge detect, pin 0 */
#define	SA1100_INTR_GPIO_1		1		/* GPIO edge detect, pin 1 */
#define	SA1100_INTR_GPIO_2		2		/* GPIO edge detect, pin 2 */
#define	SA1100_INTR_GPIO_3		3		/* GPIO edge detect, pin 3 */
#define	SA1100_INTR_GPIO_4		4		/* GPIO edge detect, pin 4 */
#define	SA1100_INTR_GPIO_5		5		/* GPIO edge detect, pin 5 */
#define	SA1100_INTR_GPIO_6		6		/* GPIO edge detect, pin 6 */
#define	SA1100_INTR_GPIO_7		7		/* GPIO edge detect, pin 7 */
#define	SA1100_INTR_GPIO_8		8		/* GPIO edge detect, pin 8 */
#define	SA1100_INTR_GPIO_9		9		/* GPIO edge detect, pin 9 */
#define	SA1100_INTR_GPIO_10		10		/* GPIO edge detect, pin 10 */
#define	SA1100_INTR_GPIO_11_27	11		/* GPIO edge detect, pin 11-27 */
#define	SA1100_INTR_LCD			12		/* LCD service request */
#define	SA1100_INTR_UDC			13		/* UDC service request */
#define	SA1100_INTR_SDLC		14		/* SDLC service request */
#define	SA1100_INTR_UART_1		15		/* UART 1 service request */
#define	SA1100_INTR_UART_2		16		/* UART 2 service request */
#define	SA1100_INTR_HSSP		16		/* HSSP service request */
#define	SA1100_INTR_UART_3		17		/* UART 3 service request */
#define	SA1100_INTR_MCP			18		/* MCP service request */
#define	SA1100_INTR_SSP			19		/* SSP service request */
#define	SA1100_INTR_DMA_0		20		/* DMA channel 0 service request */
#define	SA1100_INTR_DMA_1		21		/* DMA channel 1 service request */
#define	SA1100_INTR_DMA_2		22		/* DMA channel 2 service request */
#define	SA1100_INTR_DMA_3		23		/* DMA channel 3 service request */
#define	SA1100_INTR_DMA_4		24		/* DMA channel 4 service request */
#define	SA1100_INTR_DMA_5		25		/* DMA channel 5 service request */
#define	SA1100_INTR_TIMER_0		26		/* Timer match register 0 */
#define	SA1100_INTR_TIMER_1		27		/* Timer match register 1 */
#define	SA1100_INTR_TIMER_2		28		/* Timer match register 2 */
#define	SA1100_INTR_TIMER_3		29		/* Timer match register 3 */
#define	SA1100_INTR_RTC_TICK	30		/* RTC timer tick */
#define	SA1100_INTR_RTC_ALARM	31		/* RTC alarm */


/*
 * -------------------------------------------------------------------------
 * OS Timer registers
 * -------------------------------------------------------------------------
 */

#define	SA1100_TIMER_BASE	0x90000000	/* physical base address */
#define	SA1100_TIMER_SIZE	0x00000020

/*
 * Register offsets from SA1100_TIMER_BASE
 */
#define	SA1100_OSMR0		0x00		/* match register 0 */
#define	SA1100_OSMR1		0x04		/* match register 1 */
#define	SA1100_OSMR2		0x08		/* match register 2 */
#define	SA1100_OSMR3		0x0c		/* match register 3 */
#define	SA1100_OSCR			0x10		/* count register */
#define	SA1100_OSSR			0x14		/* status register */
#define	SA1100_OWER			0x18		/* watchdog enable register */
#define	SA1100_OIER			0x1c		/* interrupt enable register */

/*
 * OWER bits
 */
#define	SA1100_OWER_WME		0x00000001	/* enable watchdog reset on match 3 */

/*
 * OSSR bits
 */
#define	SA1100_OSSR_M0		0x00000001	/* channel 0 has matched */
#define	SA1100_OSSR_M1		0x00000002	/* channel 1 has matched */
#define	SA1100_OSSR_M2		0x00000004	/* channel 1 has matched */
#define	SA1100_OSSR_M4		0x00000008	/* channel 1 has matched */

/*
 * OIER bits
 */
#define	SA1100_OIER_E0		0x00000001	/* enable interrupt for match 0 */
#define	SA1100_OIER_E1		0x00000002	/* enable interrupt for match 1 */
#define	SA1100_OIER_E2		0x00000004	/* enable interrupt for match 2 */
#define	SA1100_OIER_E4		0x00000008	/* enable interrupt for match 3 */

/*
 * -------------------------------------------------------------------------
 * Serial ports
 * -------------------------------------------------------------------------
 */

#define	SA1100_UART1_BASE	0x80010000		/* base physical address */
#define	SA1100_UART2_BASE	0x80030000		/* base physical address */
#define	SA1100_UART3_BASE	0x80050000		/* base physical address */
#define	SA1100_UART_SIZE	0x00000024

#define	SA1100_UDC_BASE		0x80000000		/* base physical address */
#define	SA1100_HSSP_BASE	0x80040060		/* base physical address */

/*
 * Byte offsets from UART base address.
 */
#define	SA1100_UTCR0		0x00			/* control 0 */
#define	SA1100_UTCR1		0x04			/* control 1 */
#define	SA1100_UTCR2		0x08			/* control 2 */
#define	SA1100_UTCR3		0x0c			/* control 3 */
#define	SA1100_UTDR			0x14			/* data */
#define	SA1100_UTSR0		0x1c			/* status 0 */
#define	SA1100_UTSR1		0x20			/* status 1 */

/*
 * UTCR0 bits
 */
#define	SA1100_UTCR0_PE		0x01			/* parity enable */
#define	SA1100_UTCR0_OES	0x02			/* odd/even parity select */
#define	SA1100_UTCR0_SBS	0x04			/* stop bit select */
#define	SA1100_UTCR0_DSS	0x08			/* data size select */
#define	SA1100_UTCR0_SCE	0x10			/* sample clock enable */
#define	SA1100_UTCR0_RCE	0x20			/* receive clock edge select */
#define	SA1100_UTCR0_TCE	0x40			/* transmit clock edge select */

/*
 * Aliases for baud rate divisor registers
 */
#define	SA1100_UTBRD_HI		SA1100_UTCR1	/* baud rate divisor bits 8-11 */
#define	SA1100_UTBRD_LO		SA1100_UTCR2	/* baud rate divisor bits 0-7 */

/*
 * UTCR3 bits
 */
#define	SA1100_UTCR3_RXE	0x01			/* receiver enable */
#define	SA1100_UTCR3_TXE	0x02			/* transmitter enable */
#define	SA1100_UTCR3_BRK	0x04			/* break */
#define	SA1100_UTCR3_RIE	0x08			/* receive FIFO interrupt enable */
#define	SA1100_UTCR3_TIE	0x10			/* transmit FIFO interrupt enable */
#define	SA1100_UTCR3_LBM	0x20			/* loopback mode */

/*
 * UTSR0 bits
 */
#define	SA1100_UTSR0_TFS	0x01			/* transmit FIFO service request */
#define	SA1100_UTSR0_RFS	0x02			/* receive FIFO service request */
#define	SA1100_UTSR0_RID	0x04			/* receiver idle */
#define	SA1100_UTSR0_RBB	0x08			/* receiver begin of break */
#define	SA1100_UTSR0_REB	0x10			/* receiver end of break */
#define	SA1100_UTSR0_EIF	0x20			/* error in FIFO */

/*
 * UTSR1 bits
 */
#define	SA1100_UTSR1_TBY	0x01			/* transmitter busy */
#define	SA1100_UTSR1_RNE	0x02			/* receive FIFO not empty */
#define	SA1100_UTSR1_TNF	0x04			/* transmit FIFO not full */
#define	SA1100_UTSR1_PRE	0x08			/* parity error */
#define	SA1100_UTSR1_FRE	0x10			/* framing error */
#define	SA1100_UTSR1_ROR	0x20			/* receive FIFO overrun */

/*
 * -------------------------------------------------------------------------
 * MCP port
 * -------------------------------------------------------------------------
 */
#define	SA1100_MCP_BASE		0x80060000		/* base physical address */
#define	SA1100_MCP_SIZE		0x1c

/*
 * Byte offsets from SA1100_MCP_BASE
 */
#define	SA1100_MCCR0		0x00			/* control register 0 */
#define	SA1100_MCDR0		0x08			/* data register 0 */
#define	SA1100_MCDR1		0x0c			/* data register 1 */
#define	SA1100_MCDR2		0x10			/* data register 2 */
#define	SA1100_MCSR			0x18			/* status register */

/*
 * MCCR0 bits
 */
#define	SA1100_MCCR0_ASD(x)	(x)				/* audio sample rate divisor */
#define	SA1100_MCCR0_TSD(x)	((x) << 8)		/* telecom sample rate divisor */
#define	SA1100_MCCR0_MCE	0x00010000		/* mcp enable */
#define	SA1100_MCCR0_ECS	0x00020000		/* external clock select */
#define	SA1100_MCCR0_ADM	0x00040000		/* A/D sampling mode */
#define	SA1100_MCCR0_TTE	0x00080000		/* telecom tx fifo interrupt enable */
#define	SA1100_MCCR0_TRE	0x00100000		/* telecom rx fifo interrupt enable */
#define	SA1100_MCCR0_ATE	0x00200000		/* audio tx fifo interrupt enable */
#define	SA1100_MCCR0_ARE	0x00400000		/* audio rx fifo interrupt enable */
#define	SA1100_MCCR0_LBM	0x00800000		/* loopback mode */
#define	SA1100_MCCR0_ECP(x)	((x) << 24)		/* external clock prescaler */

/*
 * MCDR2 bits
 */
#define	SA1100_MCDR2_WR		0x00010000		/* write to register */
#define	SA1100_MCDR2_REG(x)	((x) << 17)

/*
 * MCSR bits
 */
#define	SA1100_MCSR_ATS		0x00000001		/* audio tx fifo request */
#define	SA1100_MCSR_ARS		0x00000002		/* audio rx fifo request */
#define	SA1100_MCSR_TTS		0x00000004		/* telecom tx fifo request */
#define	SA1100_MCSR_TRS		0x00000008		/* telecom rx fifo request */
#define	SA1100_MCSR_ATU		0x00000010		/* audio tx fifo underrun */
#define	SA1100_MCSR_ARO		0x00000020		/* audio rx fifo overrun */
#define	SA1100_MCSR_TTU		0x00000040		/* telecom tx fifo underrun */
#define	SA1100_MCSR_TRO		0x00000080		/* telecom rx fifo overrun */
#define	SA1100_MCSR_ANF		0x00000100		/* audio tx fifo not full */
#define	SA1100_MCSR_ANE		0x00000200		/* audio rx fifo not empty */
#define	SA1100_MCSR_TNF		0x00000400		/* telecom tx fifo not full */
#define	SA1100_MCSR_TNE		0x00000800		/* telecom rx fifo not empty */
#define	SA1100_MCSR_CWC		0x00001000		/* codec write completed */
#define	SA1100_MCSR_CRC		0x00002000		/* codec read completed */