ixp1200.h

Centrality Atlas II development software

/*
 * $QNXLicenseC:
 * Copyright 2008, QNX Software Systems. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License"). You 
 * may not reproduce, modify or distribute this software except in 
 * compliance with the License. You may obtain a copy of the License 
 * at: http://www.apache.org/licenses/LICENSE-2.0 
 * 
 * Unless required by applicable law or agreed to in writing, software 
 * distributed under the License is distributed on an "AS IS" basis, 
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as 
 * contributors under the License or as licensors under other terms.  
 * Please review this entire file for other proprietary rights or license 
 * notices, as well as the QNX Development Suite License Guide at 
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */




/*
 * IXP1200 processor
 *

 *
 */

#ifndef	__ARM_IXP1200_H_INCLUDED
#define	__ARM_IXP1200_H_INCLUDED

/*
 * -----------------------------------------------------------------------
 * PLL Configuration Register
 * -----------------------------------------------------------------------
 */
#define	IXP1200_PLL_CFG_BASE	0x90000c00
#define	IXP1200_PLL_CFG_SIZE	4

/*
 * PLL_CFG register CCF mask
 */
#define	IXP1200_PLL_CFG_CCF		0x1f

/*
 * -----------------------------------------------------------------------
 * GPIO
 * -----------------------------------------------------------------------
 */
#define	IXP1200_GPIO_BASE		0x90001800
#define	IXP1200_GPIO_SIZE		0x800

/*
 * Register offsets from IXP1200_GPIO_BASE
 */
#define	IXP1200_GPIO_EN			0x000
#define	IXP1200_GPIO_DATA		0x400

/*
 * GPIO_EN register bits
 */
#define	IXP1200_GPIO_EN_SA		0x00	/* SA owns GPIO 0-3 */
#define	IXP1200_GPIO_EN_IX_0	0x10	/* SA owns GPIO 1-3, IX owns GPIO 0 */
#define	IXP1200_GPIO_EN_SA_0	0x20	/* SA owns GPIO 0, IX owns GPIO 1-3 */
#define	IXP1200_GPIO_EN_IX		0x30	/* IX owns GPIO 0-3 */
#define	IXP1200_GPIO_EN_0_IN	0x00	/* GPIO 0 is input  */
#define	IXP1200_GPIO_EN_0_OUT	0x01	/* GPIO 0 is output */
#define	IXP1200_GPIO_EN_1_IN	0x00	/* GPIO 1 is input  */
#define	IXP1200_GPIO_EN_1_OUT	0x02	/* GPIO 1 is output */
#define	IXP1200_GPIO_EN_2_IN	0x00	/* GPIO 2 is input  */
#define	IXP1200_GPIO_EN_2_OUT	0x04	/* GPIO 2 is output */
#define	IXP1200_GPIO_EN_3_IN	0x00	/* GPIO 3 is input  */
#define	IXP1200_GPIO_EN_3_OUT	0x08	/* GPIO 3 is output */

/*
 * GPIO_DATA bits
 */
#define	IXP1200_GPIO_DATA_0		0x01
#define	IXP1200_GPIO_DATA_1		0x02
#define	IXP1200_GPIO_DATA_2		0x04
#define	IXP1200_GPIO_DATA_3		0x08

/*
 * -----------------------------------------------------------------------
 * RTC
 * -----------------------------------------------------------------------
 */
#define	IXP1200_RTC_BASE		0x90002000
#define	IXP1200_RTC_SIZE		0x1400

/*
 * Offsets from IXP1200_RTC_BASE
 */
#define	IXP1200_RTC_DIV		0x0000
#define	IXP1200_RTC_TINT	0x0400
#define	IXP1200_RTC_TVAL	0x0800
#define	IXP1200_RTC_CNTR	0x0c00
#define	IXP1200_RTC_ALM		0x1000

/*
 * RTC_DIV bits
 */
#define	IXP1200_RTC_DIV_RDIV(x)		((x) & 0xffff)
#define	IXP1200_RTC_DIV_WEN			0x10000		/* write enable */
#define	IXP1200_RTC_DIV_IEN			0x20000		/* interrupt enable */
#define	IXP1200_RTC_DIV_IRST		0x40000		/* reset RTC interrupt */
#define	IXP1200_RTC_DIV_IRQS		0x80000		/* 0: FIQ, 1: IRQ */

/*
 * RTC_TINT bits
 */
#define	IXP1200_RTC_TINT_RTINT(x)	((x) & 0xffff)

/*
 * RTC_TVAL bits
 */
#define	IXP1200_RTC_TVAL_TVAL(x)	((x) & 0xffff)
#define	IXP1200_RTC_TVAL_LD			0x10000		/* load RTC registers */
#define	IXP1200_RTC_TVAL_PRE		0x20000		/* 0: sysclk/128, 1: sysclk */

/*
 * -----------------------------------------------------------------------
 * UART
 * -----------------------------------------------------------------------
 */
#define	IXP1200_UART_BASE		0x90003400
#define	IXP1200_UART_SIZE		0xc00

/*
 * Register offsets from IXP1200_UART_BASE
 */
#define	IXP1200_UART_SR			0x000
#define	IXP1200_UART_CR			0x400
#define	IXP1200_UART_DR			0x800

/*
 * UART_SR bits
 */
#define	IXP1200_UART_SR_RPE		0x01		/* parity error in next char */
#define	IXP1200_UART_SR_RFE		0x02		/* framing error in next char */
#define	IXP1200_UART_SR_TXR		0x04		/* tx fifo ready */
#define	IXP1200_UART_SR_ROR		0x08		/* rx overrun */
#define	IXP1200_UART_SR_RXR		0x10		/* rx fifo ready */
#define	IXP1200_UART_SR_TXE		0x20		/* tx fifo empty */
#define	IXP1200_UART_SR_RXF		0x40		/* rx fifo full */
#define IXP1200_UART_SR_TXF		0x80		/* tx fifo full */

/*
 * UART_CR bits
 */
#define	IXP1200_UART_CR_BRK		0x00001		/* assert break */
#define	IXP1200_UART_CR_PE		0x00002		/* enable parity */
#define	IXP1200_UART_CR_PS		0x00004		/* 0=even parity, 1=odd parity */
#define	IXP1200_UART_CR_SBS		0x00008		/* 0=1 stop bit, 1=2 stop bits */
#define	IXP1200_UART_CR_RIE		0x00010		/* rx interrupt enable */
#define	IXP1200_UART_CR_DSS_5	0x00000		/* 5 data bits */
#define	IXP1200_UART_CR_DSS_6	0x00020		/* 5 data bits */
#define	IXP1200_UART_CR_DSS_7	0x00040		/* 5 data bits */
#define	IXP1200_UART_CR_DSS_8	0x00060		/* 5 data bits */
#define	IXP1200_UART_CR_UE		0x00080		/* uart enable */
#define	IXP1200_UART_CR_XIE		0x00100		/* tx interrupt enable */
#define	IXP1200_UART_CR_UIS		0x00200		/* 0=use IRQ, 1=use FIQ */

#define	IXP1200_UART_CR_BRD(x)	((x) << 16)	/* set UART_CR_BRD value */

/*
 * UART_DR bits
 */
#define	IXP1200_UART_DR_DATA(x)	((x) & 0xff)	/* mask off data */
#define	IXP1200_UART_DR_PRE		0x100			/* parity error in data */
#define	IXP1200_UART_DR_FRE		0x200			/* framing error in data */
#define	IXP1200_UART_DR_ROR		0x400			/* overrun error after data */

/*
 * -----------------------------------------------------------------------
 * Timer registers
 * -----------------------------------------------------------------------
 */
#define	IXP1200_TIMER_BASE		0x42000300
#define	IXP1200_TIMER_SIZE		0x70

/*
 * Register offsets from IXP1200_TIMER_BASE
 */
#define	IXP1200_TIMER_1_LOAD	0x00
#define	IXP1200_TIMER_1_VALUE	0x04
#define	IXP1200_TIMER_1_CONTROL	0x08
#define	IXP1200_TIMER_1_CLEAR	0x0c
#define	IXP1200_TIMER_2_LOAD	0x20
#define	IXP1200_TIMER_2_VALUE	0x24
#define	IXP1200_TIMER_2_CONTROL	0x28
#define	IXP1200_TIMER_2_CLEAR	0x2c
#define	IXP1200_TIMER_3_LOAD	0x40
#define	IXP1200_TIMER_3_VALUE	0x44
#define	IXP1200_TIMER_3_CONTROL	0x48
#define	IXP1200_TIMER_3_CLEAR	0x4c
#define	IXP1200_TIMER_4_LOAD	0x60
#define	IXP1200_TIMER_4_VALUE	0x64
#define	IXP1200_TIMER_4_CONTROL	0x68
#define	IXP1200_TIMER_4_CLEAR	0x6c

/*
 * TIMER_x_CONTROL bits
 */
#define	IXP1200_TIMER_CONTROL_STP_1		0x00	/* use core frequency */
#define	IXP1200_TIMER_CONTROL_STP_16	0x04	/* use core/16 */
#define	IXP1200_TIMER_CONTROL_STP_256	0x08	/* use core/256 */
#define	IXP1200_TIMER_CONTROL_MODE		0x40
#define	IXP1200_TIMER_CONTROL_FREE		0x00	/* free running 24-bit */
#define	IXP1200_TIMER_CONTROL_PERIODIC	0x40	/* periodic */
#define	IXP1200_TIMER_CONTROL_EN		0x80	/* enable timer */

/*