omap.h

Centrality Atlas II development software

#define OMAP_32KHZ_TIMER_TVR		0x00
#define OMAP_32KHZ_TIMER_TCR		0x04
#define OMAP_32KHZ_TIMER_CR			0x08

/* rtc */
#define OMAP_RTC_BASE				0xfffb4800
#define	OMAP_RTC_SIZE				0x54
#define OMAP_RTC_SECONDS			0x00
#define OMAP_RTC_MINUTES			0x04
#define OMAP_RTC_HOURS				0x08
#define OMAP_RTC_DAYS				0x0c
#define OMAP_RTC_MONTHS				0x10
#define OMAP_RTC_YEARS				0x14
#define OMAP_RTC_WEEKS				0x18
#define OMAP_RTC_ALARM_SECONDS		0x20
#define OMAP_RTC_ALARM_MINUTES		0x24
#define OMAP_RTC_ALARM_HOURS		0x28
#define OMAP_RTC_ALARM_DAYS			0x2c
#define OMAP_RTC_ALARM_MONTHS		0x30
#define OMAP_RTC_ALARM_YEARS		0x34
#define OMAP_RTC_CTRL				0x40
#define OMAP_RTC_STATUS				0x44
#define OMAP_RTC_INTERRUPTS			0x48
#define OMAP_RTC_COMP_LSB			0x4c
#define OMAP_RTC_COMP_MSB			0x50


/* watchdog timer */
#define OMAP_WDT_BASE				0xfffec800
#define OMAP_WDT_CNTL				0x00
#define OMAP_WDT_LOAD				0x04
#define OMAP_WDT_READ				0x04
#define OMAP_WDT_MODE				0x08

/* Secure Watchdog */
#define OMAP_SWDT_BASE				0xfffeb000
#define OMAP_SWDT_WIDR				0x00
#define OMAP_SWDT_WD_SYSCONFIG		0x10
#define OMAP_SWDT_WD_SYSSTATUS		0x14
#define OMAP_SWDT_WCLR				0x24
#define OMAP_SWDT_WCRR				0x28
#define OMAP_SWDT_WLDR				0x2c
#define OMAP_SWDT_WTGR				0x30
#define OMAP_SWDT_WWPS				0x34
#define OMAP_SWDT_WSPR				0x48

/* Bit definitions for SWDT_WWPS */
#define OMAP_SWDT_WWPS_WCLR 		0x01
#define OMAP_SWDT_WWPS_WCRR 		0x02
#define OMAP_SWDT_WWPS_WLDR 		0x04
#define OMAP_SWDT_WWPS_WTGR 		0x08
#define OMAP_SWDT_WWPS_WSPR 		0x10


/* clock, reset, and power mode control registers */
#define OMAP_CRPM_CTRL_BASE			0xfffece00
#define OMAP_ARM_CKCTL				0x00
#define OMAP_ARM_IDLECT1			0x04
#define OMAP_ARM_IDLECT2			0x08
#define OMAP_ARM_EWUPCT				0x0c
#define OMAP_ARM_RSTCT1				0x10
#define OMAP_ARM_RSTCT2				0x14
#define	OMAP_ARM_SYSST				0x18
#define OMAP_ARM_IDLECT3			0x24

/* Bit definitions for ARM_RSTCT1 */
#define OMAP_ARM_RSTCT1_SW_RST 		0x0008
#define OMAP_ARM_RSTCT1_DSP_RST 	0x0004
#define OMAP_ARM_RSTCT1_DSP_EN 		0x0002
#define OMAP_ARM_RSTCT1_ARM_RST 	0x0001

/* Bit definitions for ARM_RSTCT2 */
#define OMAP_ARM_RSTCT2_PER_EN 		0x0001

/* Bit definitions for ARM_CKCTL */
#define OMAP_ARM_CKCTL_EN_DSPCK 	0x2000

/* Bit definitions for ARM_IDLECT1 */
#define OMAP_ARM_IDLECT1_IDL_CLKOUT 	0x1000
#define OMAP_ARM_IDLECT1_SETARM_IDLE 	0x0800
#define OMAP_ARM_IDLECT1_WKUP_MODE 		0x0400
#define OMAP_ARM_IDLECT1_IDLTIM  		0x0200
#define OMAP_ARM_IDLECT1_IDLAPI 		0x0100
#define OMAP_ARM_IDLECT1_IDLDPLL 		0x0080
#define OMAP_ARM_IDLECT1_IDLIF   		0x0040
#define OMAP_ARM_IDLECT1_IDLPER  		0x0004
#define OMAP_ARM_IDLECT1_IDLXORP 		0x0002
#define OMAP_ARM_IDLECT1_IDLWDT  		0x0001

/* Bit definitions for ARM_IDLECT2 */
#define OMAP_ARM_IDLECT2_EN_CKOUT 		0x0800
#define OMAP_ARM_IDLECT2_EN_GPIOCK 		0x0200
#define OMAP_ARM_IDLECT2_DMACK_REQ 		0x0100
#define OMAP_ARM_IDLECT2_EN_TIMCK 		0x0080
#define OMAP_ARM_IDLECT2_EN_APICK 		0x0040
#define OMAP_ARM_IDLECT2_EN_LBCK 		0x0010
#define OMAP_ARM_IDLECT2_EN_LCDCK 		0x0008
#define OMAP_ARM_IDLECT2_EN_PERCK 		0x0004
#define OMAP_ARM_IDLECT2_EN_XORPCK 		0x0002
#define OMAP_ARM_IDLECT2_EN_WDTCK 		0x0001

/* Bit definitions for ARM_IDLECT3 */
#define OMAP_ARM_IDLECT3_EN_IDLTC2 		0x0020
#define OMAP_ARM_IDLECT3_EN_TC2_CK 		0x0010
#define OMAP_ARM_IDLECT3_EN_IDLTC1 		0x0008
#define OMAP_ARM_IDLECT3_EN_TC1_CK 		0x0004
#define OMAP_ARM_IDLECT3_EN_IDLOCPI		0x0002
#define OMAP_ARM_IDLECT3_EN_OCPI_CK		0x0001

/* PLL */
#define OMAP_PLL_CLKREF				12000000
#define OMAP_DPLL_CTL_REG			0xfffecf00

/* Bit definitions for DPLL_CTL_REG */
#define OMAP_DPLL_CTL_IOB 			0x2000
#define OMAP_DPLL_CTL_PLL_ENABLE 	0x0010
#define OMAP_DPLL_CTL_BYPASS_DIV 	0x000C
#define OMAP_DPLL_CTL_LOCK 			0x0001

/* OMAP Configuration Registers */
#define OMAP_CFG_BASE				0xfffe1000
#define OMAP_FUNC_MUX_CTRL_0		0x00
#define OMAP_FUNC_MUX_CTRL_1		0x04
#define OMAP_FUNC_MUX_CTRL_2		0x08
#define OMAP_COMP_MODE_CTRL_0		0x0c
#define OMAP_FUNC_MUX_CTRL_3		0x10
#define OMAP_FUNC_MUX_CTRL_4		0x14
#define OMAP_FUNC_MUX_CTRL_5		0x18
#define OMAP_FUNC_MUX_CTRL_6		0x1c
#define OMAP_FUNC_MUX_CTRL_7		0x20
#define OMAP_FUNC_MUX_CTRL_8		0x24
#define OMAP_FUNC_MUX_CTRL_9		0x28
#define OMAP_FUNC_MUX_CTRL_A		0x2c
#define OMAP_FUNC_MUX_CTRL_B		0x30
#define OMAP_FUNC_MUX_CTRL_C		0x34
#define OMAP_FUNC_MUX_CTRL_D		0x38
#define OMAP_PULL_DWN_CTRL_0		0x40
#define OMAP_PULL_DWN_CTRL_1		0x44
#define OMAP_PULL_DWN_CTRL_2		0x48
#define OMAP_PULL_DWN_CTRL_3		0x4c
#define OMAP_GATE_INH_CTRL_0		0x50
#define OMAP_VOLTAGE_CTRL_0			0x60
#define OMAP_USB_TRANSCEIVER_CTRL	0x64
#define OMAP_TEST_DBG_CTRL_0		0x70
#define OMAP_MOD_CONF_CTRL_0		0x80
#define OMAP_FUNC_MUX_CTRL_E		0x90
#define OMAP_FUNC_MUX_CTRL_F		0x94
#define OMAP_FUNC_MUX_CTRL_10		0x98
#define OMAP1610_RESET_CONTROL 		0x140  

/* Configuration Registers of OMAP5905 are different */
#define OMAP5905_MUXCR0				0x00
#define OMAP5905_MUXCR1				0x04
#define OMAP5905_MUXCR2				0x08
#define OMAP5905_DSPDMACR			0x0c
#define OMAP5905_SPDIFCR			0x10
#define OMAP5905_MODECR				0x14
#define OMAP5905_PULLCR				0x18
#define OMAP5905_CONFCR				0x1c
#define OMAP5905_SECCR				0x20
#define OMAP5905_CONFSR				0x24
#define OMAP5905_CONFREV			0x28
#define OMAP5905_LDOCR				0x2c
#define OMAP5905_TESTDBGCR			0x30

/* Bit definitions for MUXCR1 Register */
#define OMAP5905_MUXCR1_SCI1GPIO2	0x0100000
#define OMAP5905_MUXCR1_HECC2SPI3	0x4000000

/* Split Power Logic Registers */
#define	OMAP5905_SPL_WAKENCR		0x40
#define	OMAP5905_SPL_WAKSR			0x44
#define	OMAP5905_SPL_WAKCNT			0x48
#define	OMAP5905_SPL_PINCR1			0x4C
#define	OMAP5905_SPL_PINCR2			0x50
#define	OMAP5905_SPL_GPIO1MUXCR		0x54
#define	OMAP5905_SPL_SPSCR			0x58
#define	OMAP5905_SPL_ULPDCNT		0x60


/* Bit definitions for RESET_CONTROL */
#define OMAP1610_RESET_CTL_RNGIDLE 	0x40

/* Bit definitions for FUNC_MUX_CTRL_7 */
#define OMAP_FMCTL_7_ARMIO5 		0x7000
#define OMAP_FMCTL_7_ARMIO5_LOW_PWR 0x1000  /* Select low_pwr signal on armio_5 */


/* OMAP DSP Clock/Reset/Power Mode Control Registers */
#define OMAP_DSP_CTRL_BASE			0xe1008000
#define	OMAP_DSP_CKCTL				0x00
#define	OMAP_DSP_IDLECT1			0x04
#define	OMAP_DSP_IDLECT2			0x08
#define	OMAP_DSP_RSTCT2				0x14
#define	OMAP_DSP_SYSST				0x18

/* Bit definitions for DSP_IDLECT1 */
#define OMAP_DSP_IDLECT1_IDLTIM		0x0100
#define OMAP_DSP_IDLECT1_WKUP_MODE	0x0040
#define OMAP_DSP_IDLECT1_IDLDPLL	0x0020
#define OMAP_DSP_IDLECT1_IDLIF 		0x0010
#define OMAP_DSP_IDLECT1_IDLPER 	0x0004
#define OMAP_DSP_IDLECT1_IDLXORP	0x0002
#define OMAP_DSP_IDLECT1_IDLWDT		0x0001

/* Bit definitions for DSP_IDLECT2 */
#define OMAP_DSP_IDLECT2_EN_TIMCK 	0x0020
#define OMAP_DSP_IDLECT2_EN_PERCK 	0x0004
#define OMAP_DSP_IDLECT2_EN_XORPCK	0x0002
#define OMAP_DSP_IDLECT2_EN_WDTCK	0x0001

/* USB OTG */
#define OMAP_OTG_BASE				0xfffb0400
#define OTG_REV						0x00
#define OTG_SYSCON_1				0x04
#define OTG_SYSCON_2				0x08
#define OTG_CTRL					0x0c
#define OTG_IRQ_EN					0x10
#define OTG_IRQ_SRC					0x14
#define OTG_VC						0xfc

/* Bit definitions for OTG_SYSCON_2 */
#define OTG_SYSCON_2_UHOST_EN 		0x100


/* USB */
#define OMAP1610_USB_BASE 			0xfffb4000
#define OMAP1610_USB_SYSCON1 		0x18
#define OMAP1610_USB_SYSCON2 		0x1C

/* Bit definitions for USB_SYSCON1 */
#define OMAP1610_USB_SYSCON1_SOFF_DIS 	0x02

/* OCPI */
#define OMAP_OCPI_BASE				0xfffec320
#define OCPI_ADDR_FAULT				0x00
#define OCPI_MASTER_CMD_FAULT		0x04
#define OCPI_SINT_0					0x08
#define OCPI_ABORT_TYPE				0x0c
#define OCPI_SINT_1					0x10
#define OCPI_PROT					0x14
#define OCPI_SEC_MODE				0x18

/* OMAP5905 CAN */
#define OMAP5905_CAN1_REG_BASE 		0xfffba800
#define OMAP5905_CAN2_REG_BASE 		0xfffbc000
#define OMAP5905_CAN1_MEM_BASE 		0xfffbac00
#define OMAP5905_CAN2_MEM_BASE 		0xfffbc400
#define OMAP5905_CAN_REG_SIZE_HECC	0x80
#define OMAP5905_CAN_MEM_SIZE_HECC	0x200
#define OMAP5905_CAN_MEM_SIZE_SCC	0x100
#define OMAP5905_CANLAM_MEM_SIZE	0x80 
#define OMAP5905_CANMOTS_MEM_SIZE	0x80
#define OMAP5905_CANMOT0_MEM_SIZE	0x80
#define OMAP5905_CAN_NUM_MAILBOX_SCC	16
#define OMAP5905_CAN_NUM_MAILBOX_HECC	32	
#define OMAP5905_CAN_CLK_12MHZ 		12000000
#define OMAP5905_CAN_CLK_48MHZ 		48000000

/* OMAP5905 CAN Register Offsets */
#define OMAP5905_CANME 				0x00
#define OMAP5905_CANMD 				0x04
#define OMAP5905_CANTRS				0x08
#define OMAP5905_CANTRR		 		0x0C
#define OMAP5905_CANTA 				0x10
#define OMAP5905_CANAA 				0x14
#define OMAP5905_CANRMP 			0x18
#define OMAP5905_CANRML 			0x1C
#define OMAP5905_CANRFP 			0x20
#define OMAP5905_CANGAM				0x24 
#define OMAP5905_CANMC	 			0x28
#define OMAP5905_CANBTC 			0x2C
#define OMAP5905_CANES 				0x30
#define OMAP5905_CANTEC 			0x34
#define OMAP5905_CANREC 			0x38
#define OMAP5905_CANGIF0 			0x3C
#define OMAP5905_CANGIM 			0x40
#define OMAP5905_CANGIF1 			0x44
#define OMAP5905_CANMIM 			0x48
#define OMAP5905_CANMIL 			0x4C
#define OMAP5905_CANOPC 			0x50
#define OMAP5905_CANTIOC 			0x54
#define OMAP5905_CANRIOC			0x58
#define OMAP5905_CANLNT				0x5C
#define OMAP5905_CANTOC 			0x60
#define OMAP5905_CANTOS				0x64
#define OMAP5905_CANLAM				0x80 
#define OMAP5905_CANLAM0_SCC		0x80 /* SCC only */
#define OMAP5905_CANLAM3_SCC		0x8C /* SCC only */
#define OMAP5905_CANMOTS			0x100
#define OMAP5905_CANMOTO			0x180

/* Bit definitions for OMAP5905 CAN Master and Control (CANMC) Register */
#define OMAP5905_CANMC_MBNR_MASK	0x0000001F
#define OMAP5905_CANMC_SRES			0x00000020
#define OMAP5905_CANMC_STM			0x00000040
#define OMAP5905_CANMC_ABO			0x00000080
#define OMAP5905_CANMC_CDR			0x00000100
#define OMAP5905_CANMC_WUBA			0x00000200
#define OMAP5905_CANMC_DBO			0x00000400
#define OMAP5905_CANMC_PDR			0x00000800
#define OMAP5905_CANMC_CCR			0x00001000
#define OMAP5905_CANMC_SCM			0x00002000
#define OMAP5905_CANMC_LNTM			0x00004000
#define OMAP5905_CANMC_LNTC			0x00008000

/* Bit definitions for OMAP5905 CAN Error and Status (CANES) Register */
#define OMAP5905_CANES_TM			0x00000001
#define OMAP5905_CANES_RM			0x00000002
#define OMAP5905_CANES_PDA			0x00000008
#define OMAP5905_CANES_CCE			0x00000010
#define OMAP5905_CANES_SMA			0x00000020
#define OMAP5905_CANES_EW			0x00010000
#define OMAP5905_CANES_EP			0x00020000
#define OMAP5905_CANES_BO			0x00040000
#define OMAP5905_CANES_ACKE			0x00080000
#define OMAP5905_CANES_SE			0x00100000
#define OMAP5905_CANES_CRCE			0x00200000
#define OMAP5905_CANES_SA1			0x00400000
#define OMAP5905_CANES_BE			0x00800000
#define OMAP5905_CANES_FE			0x01000000

/* Bit definitions for OMAP5905 CAN Global Interrupt Mask (CANGIM) Register */
#define OMAP5905_CANGIM_I0EN		0x00000001
#define OMAP5905_CANGIM_I1EN		0x00000002
#define OMAP5905_CANGIM_SIL			0x00000004
#define OMAP5905_CANGIM_WLIM		0x00000100
#define OMAP5905_CANGIM_EPIM		0x00000200
#define OMAP5905_CANGIM_BOIM		0x00000400
#define OMAP5905_CANGIM_RMLIM		0x00000800
#define OMAP5905_CANGIM_WUIM		0x00001000
#define OMAP5905_CANGIM_WDIM		0x00002000
#define OMAP5905_CANGIM_AAIM		0x00004000
#define OMAP5905_CANGIM_TCOIM		0x00010000
#define OMAP5905_CANGIM_MAIM		0x00020000

/* Bit definitions for OMAP5905 CAN Global Interrupt Flag (CANGIF) Register */
#define OMAP5905_CANGIF_MIV_HECC	0x0000001F
#define OMAP5905_CANGIF_MIV_SCC		0x0000000F
#define OMAP5905_CANGIF_WLIF		0x00000100
#define OMAP5905_CANGIF_EPIF		0x00000200
#define OMAP5905_CANGIF_BOIF		0x00000400
#define OMAP5905_CANGIF_RMLIF		0x00000800
#define OMAP5905_CANGIF_WUIF		0x00001000
#define OMAP5905_CANGIF_WDIF		0x00002000
#define OMAP5905_CANGIF_AAIF		0x00004000
#define OMAP5905_CANGIF_GMIF		0x00008000
#define OMAP5905_CANGIF_TCOIF		0x00010000
#define OMAP5905_CANGIF_MAIF		0x00020000

/* Bit definitions for OMAP5905 CAN Transmit I/O Control (CANTIOC) Register */
#define OMAP5905_CANTIOC_TXIN		0x00000001
#define OMAP5905_CANTIOC_TXOUT		0x00000002
#define OMAP5905_CANTIOC_TXDIR		0x00000004
#define OMAP5905_CANTIOC_TXFUNC		0x00000008

/* Bit definitions for OMAP5905 CAN Transmit I/O Control (CANRIOC) Register */
#define OMAP5905_CANRIOC_RXIN		0x00000001
#define OMAP5905_CANRIOC_RXOUT		0x00000002
#define OMAP5905_CANRIOC_RXDIR		0x00000004
#define OMAP5905_CANRIOC_RXFUNC		0x00000008

/* Bit definitions for OMAP5905 CAN Bit-timing Configuration (CANBTC) Register */
#define OMAP5905_CANBTC_TSEG2_MASK		0x00000007
#define OMAP5905_CANBTC_TSEG1_MASK		0x00000078
#define OMAP5905_CANBTC_SAM				0x00000080
#define OMAP5905_CANBTC_SJW_MASK		0x00000300
#define OMAP5905_CANBTC_ERM				0x00000400
#define OMAP5905_CANBTC_BRP_MASK		0x00FF0000
#define OMAP5905_CANBTC_BRP_MAXVAL		0xFF
#define OMAP5905_CANBTC_BRP_SHIFT		16	
#define OMAP5905_CANBTC_SJW_MAXVAL		0x3
#define OMAP5905_CANBTC_SJW_SHIFT		8	
#define OMAP5905_CANBTC_TSEG2_MAXVAL	0x7
#define OMAP5905_CANBTC_TSEG2_SHIFT		0	
#define OMAP5905_CANBTC_TSEG1_MAXVAL	0xF
#define OMAP5905_CANBTC_TSEG1_SHIFT		3	
#define OMAP5905_CANBTC_DECREMENT		1			/* All values stored in CANBTC must be adjusted */
#define OMAP5905_CANBTC_SAM_BRP_MIN		5			/* Minimum BRP value before SAM can be enabled */
#define OMAP5905_CAN_BITRATE_MAX		100000000 	/* 1Mbps max bitrate, depending on bus and transceiver */

/* Bit definitions for OMAP5905 CAN Message Control Field (CANMCF) Register */
#define OMAP5905_CANMCF_DLC_BYTE0	0x0
#define OMAP5905_CANMCF_DLC_BYTE1	0x1
#define OMAP5905_CANMCF_DLC_BYTE2	0x2
#define OMAP5905_CANMCF_DLC_BYTE3	0x3
#define OMAP5905_CANMCF_DLC_BYTE4	0x4
#define OMAP5905_CANMCF_DLC_BYTE5	0x5
#define OMAP5905_CANMCF_DLC_BYTE6	0x6
#define OMAP5905_CANMCF_DLC_BYTE7	0x7
#define OMAP5905_CANMCF_DLC_BYTE8	0x8
#define OMAP5905_CANMCF_RTR			0x00000010
#define OMAP5905_CANMCF_TPL_SHIFT	8			/* Bit 8 */
#define OMAP5905_CANMCF_TPL_MAXVAL	0x3F
#define OMAP5905_CANMCF_TPL_MASK	0x00003F00

/* Bit definitions for OMAP5905 CAN Message Identifier (CANMID) Register */
#define OMAP5905_CANMID_MASK_STD	0x1FFC0000
#define OMAP5905_CANMID_MASK_EXT	0x1FFFFFFF
#define OMAP5905_CANMID_AAM			0x20000000
#define OMAP5905_CANMID_AME			0x40000000
#define OMAP5905_CANMID_IDE			0x80000000

/* Bit definitions for OMAP5905 CAN Local Acceptance Mask (CANLAM) Register */
#define OMAP5905_CANLAM_LAMI 		0x80000000
#define OMAP5905_CANLAM_MASK		0x1FFFFFFF




/* __SRCVERSION("omap.h $Rev: 169789 $"); */