mx1.h

Centrality Atlas II development software

/*
 * $QNXLicenseC:
 * Copyright 2008, QNX Software Systems. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License"). You 
 * may not reproduce, modify or distribute this software except in 
 * compliance with the License. You may obtain a copy of the License 
 * at: http://www.apache.org/licenses/LICENSE-2.0 
 * 
 * Unless required by applicable law or agreed to in writing, software 
 * distributed under the License is distributed on an "AS IS" basis, 
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as 
 * contributors under the License or as licensors under other terms.  
 * Please review this entire file for other proprietary rights or license 
 * notices, as well as the QNX Development Suite License Guide at 
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */




/*
 * MX1 processor
 *

 *
 */

#ifndef	__ARM_MX1_H_INCLUDED
#define	__ARM_MX1_H_INCLUDED

/*
 * Embedded SRAM base
 */
#define	MX1_ESRAM_BASE			0x00300000

/*
 * -------------------------------------------------------------------------
 * WatchDog Timer registers
 * -------------------------------------------------------------------------
 */
#define	MX1_WDT_BASE			0x00201000	/* Base Physical Address */
#define	MX1_WDT_SIZE			0x0C

/*
 * Register offsets from MX1_WDT_BASE
 */
#define	MX1_WDT_WCR				0x00		/* WatchDog Control Register */
#define	MX1_WDT_WSR				0x04		/* WatchDog Service Register */
#define	MX1_WDT_WSTR			0x08		/* WatchDog Status Register */


/*
 * -------------------------------------------------------------------------
 * General-Purpose Timer registers
 * -------------------------------------------------------------------------
 */

#define	MX1_TIMER1_BASE			0x00202000	/* Timer 1 BASE */
#define	MX1_TIMER2_BASE			0x00203000	/* Timer 2 BASE */
#define	MX1_TIMER_SIZE			0x00000018

/*
 * Register offsets from MX1_TIMER_BASE
 */
#define	MX1_TIMER_CTL			0x00		/* Timer Control Register */
#define	MX1_TIMER_PRER			0x04		/* Timer Prescaler Register */
#define	MX1_TIMER_CMP			0x08		/* Timer Compare Register */
#define	MX1_TIMER_CR			0x0C		/* Timer Capture Register */
#define	MX1_TIMER_CN			0x10		/* Timer Counter Register */
#define	MX1_TIMER_STAT			0x14		/* Timer Status Register */

/*
 * -------------------------------------------------------------------------
 * RTC Registers
 * -------------------------------------------------------------------------
 */
#define	MX1_RTC_BASE			0x00204000
#define	MX1_RTC_SIZE			0x28

/* 
 * RTC Registers, offset from base address 
 */
#define	MX1_RTC_HOURMIN			0x00		/* RTC Hours and Minutes Counter Register */
#define	MX1_RTC_SECONDS			0x04		/* RTC Seconds Counter Register */
#define	MX1_RTC_ALRM_HM			0x08		/* RTC Hours and Minutes Alarm Register */
#define	MX1_RTC_ALRM_SEC		0x0C		/* RTC Seconds Alarm Register */
#define	MX1_RTC_RCCTL			0x10		/* RTC Control Register */
#define	MX1_RTC_ISR				0x14		/* RTC Interrupt Status Register */
#define	MX1_RTC_IENR			0x18		/* RTC Interrupt Enable Register */
#define	MX1_RTC_STPWCH			0x1C		/* Stopwatch Minutes Register */
#define	MX1_RTC_DAYR			0x20		/* RTC Days Counter Register */
#define	MX1_RTC_DAYALARM		0x24		/* RTC Day Alarm Register */

/*
 * -------------------------------------------------------------------------
 * Serial ports
 * -------------------------------------------------------------------------
 */

/* UART1 base address */
#define	MX1_UART1_BASE			0x00206000

/* UART2 base address */
#define	MX1_UART2_BASE			0x00207000

#define	MX1_UART_SIZE			0xE0

/* UART registers, offset from base address */
#define	MX1_UART_RXDATA			0x00		/* Receiver Register */
#define	MX1_UART_TXDATA			0x40		/* Transmitter Register */
#define	MX1_UART_CR1			0x80		/* Control Register 1 */
#define	MX1_UART_CR2			0x84		/* Control Register 2 */
#define	MX1_UART_CR3			0x88		/* Control Register 3 */
#define	MX1_UART_CR4			0x8C		/* Control Register 4 */
#define	MX1_UART_FCR			0x90		/* FIFO Control Register */
#define	MX1_UART_SR1			0x94		/* Status Register 1 */
#define	MX1_UART_SR2			0x98		/* Status Register 2 */
#define	MX1_UART_ESC			0x9C		/* Escape Character Register */
#define	MX1_UART_TIM			0xA0		/* Escape Timer Register */
#define	MX1_UART_BIR			0xA4		/* BRM Incremental Register */
#define	MX1_UART_BMR			0xA8		/* BRM Modulator Register */
#define	MX1_UART_BRC			0xAC		/* Baud Rate Count Register */
#define	MX1_UART_BIPR1			0xB0		/* BRM Incremental Preset Register 1 */
#define	MX1_UART_BIPR2			0xB4		/* BRM Incremental Preset Register 2 */
#define	MX1_UART_BIPR3			0xB8		/* BRM Incremental Preset Register 3 */
#define	MX1_UART_BIPR4			0xBC		/* BRM Incremental Preset Register 4 */
#define	MX1_UART_BMPR1			0xC0		/* BRM Modulator Preset Register */
#define	MX1_UART_BMPR2			0xC4		/* BRM Modulator Preset Register */
#define	MX1_UART_BMPR3			0xC8		/* BRM Modulator Preset Register */
#define	MX1_UART_BMPR4			0xCC		/* BRM Modulator Preset Register */
#define	MX1_UART_TS				0xD0		/* Test Register */

/* 
 * Receiver Register bits
 */
#define	MX1_URXD_CHARRDY		(1<<15)		/* Character Ready */
#define	MX1_URXD_ERR			(1<<14)		/* Error Detect */
#define	MX1_URXD_OVERRUN		(1<<13)		/* Receiver Overrun */
#define	MX1_URXD_FRMERR			(1<<12)		/* Frame Error */
#define	MX1_URXD_BRK			(1<<11)		/* BREAK detect */
#define	MX1_URXD_PRERR			(1<<10)		/* Parity Error */

/* 
 * Control Register 1 bits
 */
#define	MX1_UCR1_ADEN			(1<<15)		/* Automatic Baud Rate Detection Interrupt Enable */
#define	MX1_UCR1_ADBR			(1<<14)		/* Automatic Detection of Baud Rate */
#define	MX1_UCR1_TRDYEN			(1<<13)		/* Transmitter Ready Interrupt Enable */
#define	MX1_UCR1_IDEN			(1<<12)		/* Idle Condition Detected Interrupt */
#define	MX1_UCR1_ICD_MASK		(3<<10)		/* Idle Condition Detect Mask */
#define	MX1_UCR1_RRDYEN			(1<<9)		/* Receiver Ready Interrupt Enable */
#define	MX1_UCR1_RDMAEN			(1<<8)		/* Receive Ready DMA Enable */
#define	MX1_UCR1_IREN			(1<<7)		/* Infrared Interface Enable */
#define	MX1_UCR1_TXMPTYEN		(1<<6)		/* Transmitter Empty Interrupt Enable */
#define	MX1_UCR1_RTSDEN			(1<<5)		/* RTS Delta Interrupt Enable */
#define	MX1_UCR1_SNDBRK			(1<<4)		/* Send BREAK */
#define	MX1_UCR1_TDMAEN			(1<<3)		/* Transmitter Ready DMA Enable */
#define	MX1_UCR1_UARTCLKEN		(1<<2)		/* UART Clock Enable */
#define	MX1_UCR1_DOZE			(1<<1)		/* UART DOZE State Control */
#define	MX1_UCR1_UARTEN			(1<<0)		/* UART Enable */

/* 
 * Control Register 2 bits
 */
#define	MX1_UCR2_ESCI			(1<<15)		/* Escape Sequence Interrupt Enable */
#define	MX1_UCR2_IRTS			(1<<14)		/* Ignore UART RTS pin */
#define	MX1_UCR2_CTSC			(1<<13)		/* UART CTS pin Control */
#define	MX1_UCR2_CTS			(1<<12)		/* Clear To Send */
#define	MX1_UCR2_ESCEN			(1<<11)		/* Escape Enable */
#define	MX1_UCR2_RTEC_MASK		(3<<9)		/* Request to Send Edge Control Mask */
#define	MX1_UCR2_PREN			(1<<8)		/* Parity Enable */
#define	MX1_UCR2_PROE			(1<<7)		/* Parity Odd/Even */
#define	MX1_UCR2_STPB			(1<<6)		/* Stop Bit */
#define	MX1_UCR2_WS				(1<<5)		/* Word Size */
#define	MX1_UCR2_RTSEN			(1<<4)		/* Request to Send Interrupt Enable */
#define	MX1_UCR2_TXEN			(1<<2)		/* Transmitter Enable */
#define	MX1_UCR2_RXEN			(1<<1)		/* Receiver Enable */
#define	MX1_UCR2_SRST			(1<<0)		/* Software Reset */

/* 
 * Control Register 3 bits
 */
#define	MX1_UCR3_DPEC_MASK		(3<<14)		/* DTR Interrupt Edge Control */
#define	MX1_UCR3_DTREN			(1<<13)		/* Data Terminal Ready Interrupt Enable */
#define	MX1_UCR3_PARERREN		(1<<12)		/* Parity Error Interrupt Enable */
#define	MX1_UCR3_FRAERREN		(1<<11)		/* Frame Error Interrupt Enable */
#define	MX1_UCR3_DSR			(1<<10)		/* Data Set Ready */
#define	MX1_UCR3_DCD			(1<<9)		/* Data Carrier Detect */
#define	MX1_UCR3_RI				(1<<8)		/* Ring Indicator */
#define	MX1_UCR3_RXDSEN			(1<<6)		/* Receive Status Interrupt Enable */
#define	MX1_UCR3_AIRINTEN		(1<<5)		/* Asynchronous IR WAKE Interrupt Enable */
#define	MX1_UCR3_AWAKEN			(1<<4)		/* Asynchronous WAKE Interrupt Enable */
#define	MX1_UCR3_REF25			(1<<3)		/* Reference Frequency 25 MHz */
#define	MX1_UCR3_REF20			(1<<2)		/* Reference Frequency 30 MHz */
#define	MX1_UCR3_INVT			(1<<1)		/* Inverted Infrared Transmission */
#define	MX1_UCR3_BPEN			(1<<0)		/* Preset Registers Enable */

/* 
 * Control Register 4 bits
 */