📄 at91sam9263.h
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/* CR */#define AT91SAM9263_DBGU_CR_RSTSTA 0x00000100#define AT91SAM9263_DBGU_CR_TXDIS 0x00000080#define AT91SAM9263_DBGU_CR_TXEN 0x00000040#define AT91SAM9263_DBGU_CR_RXDIS 0x00000020#define AT91SAM9263_DBGU_CR_RXEN 0x00000010#define AT91SAM9263_DBGU_CR_RSTTX 0x00000008#define AT91SAM9263_DBGU_CR_RSTRX 0x00000004 /* MR */#define AT91SAM9263_DBGU_MR_CHMODE(mode) ((mode & 3) << 14) #define AT91SAM9263_DBGU_MR_CHMODE_MASK AT91SAM9263_DBGU_MR_CHMODE(3) #define AT91SAM9263_DBGU_MR_CHMODE_NORMAL AT91SAM9263_DBGU_MR_CHMODE(0) #define AT91SAM9263_DBGU_MR_CHMODE_AUTO_ECHO AT91SAM9263_DBGU_MR_CHMODE(1) #define AT91SAM9263_DBGU_MR_CHMODE_LOCAL_LOOPB AT91SAM9263_DBGU_MR_CHMODE(2) #define AT91SAM9263_DBGU_MR_CHMODE_REMOTE_LOOPB AT91SAM9263_DBGU_MR_CHMODE(3)#define AT91SAM9263_DBGU_MR_PAR(par) ((par & 7) << 9) #define AT91SAM9263_DBGU_MR_PAR_MASK AT91SAM9263_DBGU_MR_PAR(7) #define AT91SAM9263_DBGU_MR_PAR_EVEN AT91SAM9263_DBGU_MR_PAR(0) #define AT91SAM9263_DBGU_MR_PAR_ODD AT91SAM9263_DBGU_MR_PAR(1) #define AT91SAM9263_DBGU_MR_PAR_SPACE AT91SAM9263_DBGU_MR_PAR(2) #define AT91SAM9263_DBGU_MR_PAR_MARK AT91SAM9263_DBGU_MR_PAR(3) #define AT91SAM9263_DBGU_MR_PAR_NONE AT91SAM9263_DBGU_MR_PAR(4) /* IER, IDR, IMR & SR*/#define AT91SAM9263_DBGU_IE_SR_COMMRX 0x80000000#define AT91SAM9263_DBGU_IE_SR_COMMTX 0x40000000#define AT91SAM9263_DBGU_IE_SR_RXBUFF 0x00001000#define AT91SAM9263_DBGU_IE_SR_TXBUFFE 0x00000800#define AT91SAM9263_DBGU_IE_SR_TXEMPTY 0x00000200#define AT91SAM9263_DBGU_IE_SR_PARE 0x00000080#define AT91SAM9263_DBGU_IE_SR_FRAME 0x00000040#define AT91SAM9263_DBGU_IE_SR_OVERE 0x00000020#define AT91SAM9263_DBGU_IE_SR_ENDTX 0x00000010#define AT91SAM9263_DBGU_IE_SR_ENDRX 0x00000008#define AT91SAM9263_DBGU_IE_SR_TXRDY 0x00000002#define AT91SAM9263_DBGU_IE_SR_RXRDY 0x00000001 /* RHR & THR */#define AT91SAM9263_DBGU_RHR_THR_CHAR_MASK 0x000000ff /* BRGR */#define AT91SAM9263_DBGU_BRGR_CD_MASK 0x0000ffff #define AT91SAM9263_DBGU_BRGR_CD_DISABLE 0x00000000 #define AT91SAM9263_DBGU_BRGR_CD_MCK 0x00000001 /* CIDR */#define AT91SAM9263_DBGU_CIDR_EXT 0x80000000#define AT91SAM9263_DBGU_CIDR_NVPTYP 0x70000000#define AT91SAM9263_DBGU_CIDR_ARCH 0x0ff00000#define AT91SAM9263_DBGU_CIDR_SRAMSIZ 0x000f0000#define AT91SAM9263_DBGU_CIDR_NVPSIZ2 0x0000f000#define AT91SAM9263_DBGU_CIDR_NVPSIZ 0x00000f00#define AT91SAM9263_DBGU_CIDR_EPROC 0x000000e0#define AT91SAM9263_DBGU_CIDR_VERSION 0x0000001f /* EXID */#define AT91SAM9263_DBGU_EXID_MASK 0xffffffff /* FNR */#define AT91SAM9263_DBGU_FNR_FNTRST 0x00000001 /* * Two-Wire Interface (TWI) */ /* Control Register (CR) */#define AT91SAM9263_TWI_CR_SWRST 0x00000080#define AT91SAM9263_TWI_CR_MSDIS 0x00000008#define AT91SAM9263_TWI_CR_MSEN 0x00000004#define AT91SAM9263_TWI_CR_STOP 0x00000002#define AT91SAM9263_TWI_CR_START 0x00000001 /* Master Mode Register (MMR) */#define AT91SAM9263_TWI_MMR_DADR 0x007f0000#define AT91SAM9263_TWI_MMR_MREAD 0x00001000#define AT91SAM9263_TWI_MMR_IADRSZ 0x00000300 /* Internal Address Register (IADR) */#define AT91SAM9263_TWI_IADR0 0x000000ff#define AT91SAM9263_TWI_IADR1 0x0000ff00#define AT91SAM9263_TWI_IADR2 0x00ff0000#define AT91SAM9263_TWI_IADR_SET(byte,val) ((val & 0xff) << (8 * byte)) /* Clock Waveform Generator Register (CWGR) */#define AT91SAM9263_TWI_CWGR_CKDIV 0x00070000#define AT91SAM9263_TWI_CWGR_CHDIV 0x0000ff00#define AT91SAM9263_TWI_CWGR_CLDIV 0x000000ff /* Status Register (SR )and Interrupt Enable,Disable & Mask Register (IER, IDR & IMR) */#define AT91SAM9263_TWI_SR_NACK 0x00000100#define AT91SAM9263_TWI_SR_TXRDY 0x00000004#define AT91SAM9263_TWI_SR_RXRDY 0x00000002#define AT91SAM9263_TWI_SR_TXCOMP 0x00000001 /* Received & Transmit Holding Register(RHR & THR)*/#define AT91SAM9263_TWI_HR_DATA 0x000000ff /* * Serial Peripheral Interface (SPI) */ /* Control Register (CR) */#define AT91SAM9263_SPI_CR_LASTXFER 0x01000000#define AT91SAM9263_SPI_CR_SWRST 0x00000080#define AT91SAM9263_SPI_CR_SPIDIS 0x00000002#define AT91SAM9263_SPI_CR_SPIEN 0x00000001 /* Mode Register (MR) */#define AT91SAM9263_SPI_MR_DLYBCS(dlybcs) ((dlybcs & 0xff) << 24)#define AT91SAM9263_SPI_MR_PCS(pcs) ((pcs & 0xf) << 16)#define AT91SAM9263_SPI_MR_LLB 0x00000080#define AT91SAM9263_SPI_MR_MODFDIS 0x00000010#define AT91SAM9263_SPI_MR_PCSDEC 0x00000004#define AT91SAM9263_SPI_MR_PS 0x00000002#define AT91SAM9263_SPI_MR_MSTR 0x00000001 /* Receive Data Register (RDR) */#define AT91SAM9263_SPI_RDR_PCS(pcs) ((pcs & 0xf) << 16)#define AT91SAM9263_SPI_RDR_RD 0x0000ffff /* Transmit Data Register (TDR) */#define AT91SAM9263_SPI_TDR_LASTXFER 0x00010000#define AT91SAM9263_SPI_TDR_PCS(pcs) ((pcs & 0xf) << 16)#define AT91SAM9263_SPI_TDR_TD 0x0000ffff /* Status Register (SR )and Interrupt Enable,Disable & Mask Register (IER, IDR & IMR) */#define AT91SAM9263_SPI_SR_SPIENS 0x00010000 // Status Register Only */#define AT91SAM9263_SPI_SR_TDEMPTY 0x00000200#define AT91SAM9263_SPI_SR_NSSR 0x00000100#define AT91SAM9263_SPI_SR_TXBUFE 0x00000080#define AT91SAM9263_SPI_SR_RXBUFF 0x00000040#define AT91SAM9263_SPI_SR_ENDTX 0x00000020#define AT91SAM9263_SPI_SR_ENDRX 0x00000010#define AT91SAM9263_SPI_SR_OVRES 0x00000008#define AT91SAM9263_SPI_SR_MODF 0x00000004#define AT91SAM9263_SPI_SR_TDRE 0x00000002#define AT91SAM9263_SPI_SR_RDRF 0x00000001 /* Chip Select Register 0, 1, 2 & 3 (CSR0 - CSR3) */#define AT91SAM9263_SPI_CSRx_DLYBCT(dlybct) ((dlybct & 0xff) << 24) #define AT91SAM9263_SPI_CSRx_DLYBS(dlybs) ((dlybs & 0xff) << 16)#define AT91SAM9263_SPI_CSRx_SCBR(scbr) ((scbr & 0xff) << 8)#define AT91SAM9263_SPI_CSRx_BITS(bits) ((bits & 0xf) << 4)#define AT91SAM9263_SPI_CSRx_CSAAT 0x00000008#define AT91SAM9263_SPI_CSRx_NCPHA 0x00000002#define AT91SAM9263_SPI_CSRx_CPOL 0x00000001 /* * PIO Controller A Register's bit Definition. */#define AT91SAM9263_PIO_PA0_A_MCI0_DA0 (1 << 0) #define AT91SAM9263_PIO_PA0_B_SPI0_MISO (1 << 0)#define AT91SAM9263_PIO_PA1_A_MCI0_CDA (1 << 1)#define AT91SAM9263_PIO_PA1_B_SPI0_MOSI (1 << 1)#define AT91SAM9263_PIO_PA2_A_ (1 << 2)#define AT91SAM9263_PIO_PA2_B_SPI0_SPCK (1 << 2)#define AT91SAM9263_PIO_PA3_A_MCI0_DA1 (1 << 3)#define AT91SAM9263_PIO_PA3_B_SPI0_NPCS1 (1 << 3)#define AT91SAM9263_PIO_PA4_A_MCI0_DA2 (1 << 4)#define AT91SAM9263_PIO_PA4_B_SPI0_NPCS2 (1 << 4)#define AT91SAM9263_PIO_PA5_A_MCI0_DA3 (1 << 5)#define AT91SAM9263_PIO_PA5_B_SPI0_NPCS3 (1 << 5)#define AT91SAM9263_PIO_PA6_A_MCI1_CK (1 << 6)#define AT91SAM9263_PIO_PA6_B_ (1 << 6)#define AT91SAM9263_PIO_PA7_A_MCI1_CDA (1 << 7)#define AT91SAM9263_PIO_PA7_B_ (1 << 7)#define AT91SAM9263_PIO_PA8_A_MCI1_DA0 (1 << 8)#define AT91SAM9263_PIO_PA8_B_ (1 << 8)#define AT91SAM9263_PIO_PA9_A_MCI1_DA1 (1 << 9)#define AT91SAM9263_PIO_PA9_B_ (1 << 9)#define AT91SAM9263_PIO_PA10_A_MCI1_DA2 (1 << 10)#define AT91SAM9263_PIO_PA10_B_ (1 << 10)#define AT91SAM9263_PIO_PA11_A_MCI1_DA3 (1 << 11)#define AT91SAM9263_PIO_PA11_B_ (1 << 11)#define AT91SAM9263_PIO_PA12_A_MCI0_CK (1 << 12)#define AT91SAM9263_PIO_PA12_B_ (1 << 12)#define AT91SAM9263_PIO_PA13_A_CANTX (1 << 13)#define AT91SAM9263_PIO_PA13_B_PCK0 (1 << 13)#define AT91SAM9263_PIO_PA14_A_CANRX (1 << 14)#define AT91SAM9263_PIO_PA14_B_IRQ0 (1 << 14)#define AT91SAM9263_PIO_PA15_A_TCLK2 (1 << 15)#define AT91SAM9263_PIO_PA15_B_IRQ1 (1 << 15)#define AT91SAM9263_PIO_PA16_A_MCI0_CDB (1 << 16)#define AT91SAM9263_PIO_PA16_B_EBI1_D16 (1 << 16)#define AT91SAM9263_PIO_PA17_A_MCI0_DB0 (1 << 17)#define AT91SAM9263_PIO_PA17_B_EBI1_D17 (1 << 17)#define AT91SAM9263_PIO_PA18_A_MCI0_DB1 (1 << 18)#define AT91SAM9263_PIO_PA18_B_EBI1_D18 (1 << 18)#define AT91SAM9263_PIO_PA19_A_MCI0_DB2 (1 << 19)#define AT91SAM9263_PIO_PA19_B_EBI1_D19 (1 << 19)#define AT91SAM9263_PIO_PA20_A_MCI0_DB3 (1 << 20)#define AT91SAM9263_PIO_PA20_B_EBI1_D20 (1 << 20)#define AT91SAM9263_PIO_PA21_A_MCI1_CDB (1 << 21)#define AT91SAM9263_PIO_PA21_B_EBI1_D21 (1 << 21)#define AT91SAM9263_PIO_PA22_A_MCI1_DB0 (1 << 22)#define AT91SAM9263_PIO_PA22_B_EBI1_D22 (1 << 22)#define AT91SAM9263_PIO_PA23_A_MCI1_DB1 (1 << 23)#define AT91SAM9263_PIO_PA23_B_EBI1_D23 (1 << 23)#define AT91SAM9263_PIO_PA24_A_MCI1_DB2 (1 << 24)#define AT91SAM9263_PIO_PA24_B_EBI1_D24 (1 << 24)#define AT91SAM9263_PIO_PA25_A_MCI1_DB3 (1 << 25)#define AT91SAM9263_PIO_PA25_B_EBI1_D25 (1 << 25)#define AT91SAM9263_PIO_PA26_A_TXD0 (1 << 26)#define AT91SAM9263_PIO_PA26_B_EBI1_D26 (1 << 26)#define AT91SAM9263_PIO_PA27_A_RXD0 (1 << 27)#define AT91SAM9263_PIO_PA27_B_EBI1_D27 (1 << 27)#define AT91SAM9263_PIO_PA28_A_RTS0 (1 << 28)#define AT91SAM9263_PIO_PA28_B_EBI1_D28 (1 << 28)#define AT91SAM9263_PIO_PA29_A_CTS0 (1 << 29)#define AT91SAM9263_PIO_PA29_B_EBI1_D29 (1 << 29)#define AT91SAM9263_PIO_PA30_A_SCK0 (1 << 30)#define AT91SAM9263_PIO_PA30_B_EBI1_D30 (1 << 30)#define AT91SAM9263_PIO_PA31_A_DMARQ0 (1 << 31)#define AT91SAM9263_PIO_PA31_B_EBI1_D31 (1 << 31)/* * PIO Controller B Register's bit Definition. */#define AT91SAM9263_PIO_PB0_A_AC97FS (1 << 0) #define AT91SAM9263_PIO_PB0_B_TF0 (1 << 0)#define AT91SAM9263_PIO_PB1_A_AC97CK (1 << 1)#define AT91SAM9263_PIO_PB1_B_TK0 (1 << 1)#define AT91SAM9263_PIO_PB2_A_AC97TX (1 << 2)#define AT91SAM9263_PIO_PB2_B_TD0 (1 << 2)#define AT91SAM9263_PIO_PB3_A_AC97RX (1 << 3)#define AT91SAM9263_PIO_PB3_B_RD0 (1 << 3)#define AT91SAM9263_PIO_PB4_A_TWD (1 << 4)#define AT91SAM9263_PIO_PB4_B_RK0 (1 << 4)#define AT91SAM9263_PIO_PB5_A_TWCK (1 << 5)#define AT91SAM9263_PIO_PB5_B_RF0 (1 << 5)#define AT91SAM9263_PIO_PB6_A_TF1 (1 << 6)#define AT91SAM9263_PIO_PB6_B_DMARQ1 (1 << 6)#define AT91SAM9263_PIO_PB7_A_TK1 (1 << 7)#define AT91SAM9263_PIO_PB7_B_PWM0 (1 << 7)#define AT91SAM9263_PIO_PB8_A_TD1 (1 << 8)#define AT91SAM9263_PIO_PB8_B_PWM1 (1 << 8)#define AT91SAM9263_PIO_PB9_A_RD1 (1 << 9)#define AT91SAM9263_PIO_PB9_B_LCDCC (1 << 9)#define AT91SAM9263_PIO_PB10_A_RK1 (1 << 10)#define AT91SAM9263_PIO_PB10_B_PCK1 (1 << 10)#define AT91SAM9263_PIO_PB11_A_RF1 (1 << 11)#define AT91SAM9263_PIO_PB11_B_SPI0_NPCS3 (1 << 11)#define AT91SAM9263_PIO_PB12_A_SPI1_MISO (1 << 12)#define AT91SAM9263_PIO_PB12_B_ (1 << 12)#define AT91SAM9263_PIO_PB13_A_SPI1_MOSI (1 << 13)#define AT91SAM9263_PIO_PB13_B_ (1 << 13)⌨️ 快捷键说明
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