📄 at91sam9263.h
字号:
#define AT91SAM9263_SDRAMC_LPR 0x10#define AT91SAM9263_SDRAMC_IER 0x14#define AT91SAM9263_SDRAMC_IDR 0x18#define AT91SAM9263_SDRAMC_IMR 0x1c#define AT91SAM9263_SDRAMC_ISR 0x20#define AT91SAM9263_SDRAMC_MDR 0x24 /* Static Memory Controller (SMC) */#define AT91SAM9263_SMC_SIZE 0x80#define AT91SAM9263_SMC_SETUP(CS_NUM) (0x00 + CS_NUM*0x10)#define AT91SAM9263_SMC_PULSE(CS_NUM) (0x04 + CS_NUM*0x10)#define AT91SAM9263_SMC_CYCLE(CS_NUM) (0x08 + CS_NUM*0x10)#define AT91SAM9263_SMC_MODE(CS_NUM) (0x0c + CS_NUM*0x10) /* Bus Matrix (MATRIX) */#define AT91SAM9263_MATRIX_SIZE 0x110#define AT91SAM9263_MATRIX_MCFG0 0x000#define AT91SAM9263_MATRIX_MCFG1 0x004#define AT91SAM9263_MATRIX_MCFG2 0x008#define AT91SAM9263_MATRIX_MCFG3 0x00c#define AT91SAM9263_MATRIX_MCFG4 0x010#define AT91SAM9263_MATRIX_MCFG5 0x014#define AT91SAM9263_MATRIX_MCFG6 0x018#define AT91SAM9263_MATRIX_MCFG7 0x01c#define AT91SAM9263_MATRIX_MCFG8 0x020#define AT91SAM9263_MATRIX_SCFG0 0x40#define AT91SAM9263_MATRIX_SCFG1 0x44#define AT91SAM9263_MATRIX_SCFG2 0x48#define AT91SAM9263_MATRIX_SCFG3 0x4c#define AT91SAM9263_MATRIX_SCFG4 0x50#define AT91SAM9263_MATRIX_SCFG5 0x54#define AT91SAM9263_MATRIX_SCFG6 0x58#define AT91SAM9263_MATRIX_SCFG7 0x5c#define AT91SAM9263_MATRIX_PRAS0 0x080#define AT91SAM9263_MATRIX_PRBS0 0x084#define AT91SAM9263_MATRIX_PRAS1 0x088#define AT91SAM9263_MATRIX_PRBS1 0x08c#define AT91SAM9263_MATRIX_PRAS2 0x090#define AT91SAM9263_MATRIX_PRBS2 0x094#define AT91SAM9263_MATRIX_PRAS3 0x098#define AT91SAM9263_MATRIX_PRBS3 0x09c#define AT91SAM9263_MATRIX_PRAS4 0x0a0#define AT91SAM9263_MATRIX_PRBS4 0x0a4#define AT91SAM9263_MATRIX_PRAS5 0x0a8#define AT91SAM9263_MATRIX_PRBS5 0x0ac#define AT91SAM9263_MATRIX_PRAS6 0x0b0#define AT91SAM9263_MATRIX_PRBS6 0x0b4#define AT91SAM9263_MATRIX_PRAS7 0x0b8#define AT91SAM9263_MATRIX_PRBS7 0x0bc#define AT91SAM9263_MATRIX_MRCR 0x100 /* Chip Configuration (CCFG) */#define AT91SAM9263_CCFG_SIZE 0xf0#define AT91SAM9263_CCFG_MATRIX_TCMR 0x04#define AT91SAM9263_CCFG_EBI0_CSA 0x10#define AT91SAM9263_CCFG_EBI1_CSA 0x14/* (DBGU) */#define AT91SAM9263_DBGU_SIZE 0x4c#define AT91SAM9263_DBGU_CR 0x00#define AT91SAM9263_DBGU_MR 0x04#define AT91SAM9263_DBGU_IER 0x08#define AT91SAM9263_DBGU_IDR 0x0c#define AT91SAM9263_DBGU_IMR 0x10#define AT91SAM9263_DBGU_SR 0x14#define AT91SAM9263_DBGU_RHR 0x18#define AT91SAM9263_DBGU_THR 0x1c#define AT91SAM9263_DBGU_BRGR 0x20#define AT91SAM9263_DBGU_CIDR 0x40#define AT91SAM9263_DBGU_EXID 0x44#define AT91SAM9263_DBGU_FNR 0x48 /* Advanced Interrupt Controller (AIC) */#define AT91SAM9263_AIC_SIZE 0x200#define AT91SAM9263_AIC_SMR(x) (0x4*x)#define AT91SAM9263_AIC_SMR0 AT91SAM9263_AIC_SMR(0 )#define AT91SAM9263_AIC_SMR1 AT91SAM9263_AIC_SMR(1 )#define AT91SAM9263_AIC_SMR2 AT91SAM9263_AIC_SMR(2 )#define AT91SAM9263_AIC_SMR3 AT91SAM9263_AIC_SMR(3 )#define AT91SAM9263_AIC_SMR4 AT91SAM9263_AIC_SMR(4 )#define AT91SAM9263_AIC_SMR5 AT91SAM9263_AIC_SMR(5 )#define AT91SAM9263_AIC_SMR6 AT91SAM9263_AIC_SMR(6 )#define AT91SAM9263_AIC_SMR7 AT91SAM9263_AIC_SMR(7 )#define AT91SAM9263_AIC_SMR8 AT91SAM9263_AIC_SMR(8 )#define AT91SAM9263_AIC_SMR9 AT91SAM9263_AIC_SMR(9 )#define AT91SAM9263_AIC_SMR10 AT91SAM9263_AIC_SMR(10)#define AT91SAM9263_AIC_SMR11 AT91SAM9263_AIC_SMR(11)#define AT91SAM9263_AIC_SMR12 AT91SAM9263_AIC_SMR(12)#define AT91SAM9263_AIC_SMR13 AT91SAM9263_AIC_SMR(13)#define AT91SAM9263_AIC_SMR14 AT91SAM9263_AIC_SMR(14)#define AT91SAM9263_AIC_SMR15 AT91SAM9263_AIC_SMR(15)#define AT91SAM9263_AIC_SMR16 AT91SAM9263_AIC_SMR(16)#define AT91SAM9263_AIC_SMR17 AT91SAM9263_AIC_SMR(17)#define AT91SAM9263_AIC_SMR18 AT91SAM9263_AIC_SMR(18)#define AT91SAM9263_AIC_SMR19 AT91SAM9263_AIC_SMR(19)#define AT91SAM9263_AIC_SMR20 AT91SAM9263_AIC_SMR(20)#define AT91SAM9263_AIC_SMR21 AT91SAM9263_AIC_SMR(21)#define AT91SAM9263_AIC_SMR22 AT91SAM9263_AIC_SMR(22)#define AT91SAM9263_AIC_SMR23 AT91SAM9263_AIC_SMR(23)#define AT91SAM9263_AIC_SMR24 AT91SAM9263_AIC_SMR(24)#define AT91SAM9263_AIC_SMR25 AT91SAM9263_AIC_SMR(25)#define AT91SAM9263_AIC_SMR26 AT91SAM9263_AIC_SMR(26)#define AT91SAM9263_AIC_SMR27 AT91SAM9263_AIC_SMR(27)#define AT91SAM9263_AIC_SMR28 AT91SAM9263_AIC_SMR(28)#define AT91SAM9263_AIC_SMR29 AT91SAM9263_AIC_SMR(29)#define AT91SAM9263_AIC_SMR30 AT91SAM9263_AIC_SMR(30)#define AT91SAM9263_AIC_SMR31 AT91SAM9263_AIC_SMR(31)#define AT91SAM9263_AIC_SVR(x) (0x4*x + 0x80)#define AT91SAM9263_AIC_SVR0 AT91SAM9263_AIC_SVR(0 )#define AT91SAM9263_AIC_SVR1 AT91SAM9263_AIC_SVR(1 )#define AT91SAM9263_AIC_SVR2 AT91SAM9263_AIC_SVR(2 )#define AT91SAM9263_AIC_SVR3 AT91SAM9263_AIC_SVR(3 )#define AT91SAM9263_AIC_SVR4 AT91SAM9263_AIC_SVR(4 )#define AT91SAM9263_AIC_SVR5 AT91SAM9263_AIC_SVR(5 )#define AT91SAM9263_AIC_SVR6 AT91SAM9263_AIC_SVR(6 )#define AT91SAM9263_AIC_SVR7 AT91SAM9263_AIC_SVR(7 )#define AT91SAM9263_AIC_SVR8 AT91SAM9263_AIC_SVR(8 )#define AT91SAM9263_AIC_SVR9 AT91SAM9263_AIC_SVR(9 )#define AT91SAM9263_AIC_SVR10 AT91SAM9263_AIC_SVR(10)#define AT91SAM9263_AIC_SVR11 AT91SAM9263_AIC_SVR(11)#define AT91SAM9263_AIC_SVR12 AT91SAM9263_AIC_SVR(12)#define AT91SAM9263_AIC_SVR13 AT91SAM9263_AIC_SVR(13)#define AT91SAM9263_AIC_SVR14 AT91SAM9263_AIC_SVR(14)#define AT91SAM9263_AIC_SVR15 AT91SAM9263_AIC_SVR(15)#define AT91SAM9263_AIC_SVR16 AT91SAM9263_AIC_SVR(16)#define AT91SAM9263_AIC_SVR17 AT91SAM9263_AIC_SVR(17)#define AT91SAM9263_AIC_SVR18 AT91SAM9263_AIC_SVR(18)#define AT91SAM9263_AIC_SVR19 AT91SAM9263_AIC_SVR(19)#define AT91SAM9263_AIC_SVR20 AT91SAM9263_AIC_SVR(20)#define AT91SAM9263_AIC_SVR21 AT91SAM9263_AIC_SVR(21)#define AT91SAM9263_AIC_SVR22 AT91SAM9263_AIC_SVR(22)#define AT91SAM9263_AIC_SVR23 AT91SAM9263_AIC_SVR(23)#define AT91SAM9263_AIC_SVR24 AT91SAM9263_AIC_SVR(24)#define AT91SAM9263_AIC_SVR25 AT91SAM9263_AIC_SVR(25)#define AT91SAM9263_AIC_SVR26 AT91SAM9263_AIC_SVR(26)#define AT91SAM9263_AIC_SVR27 AT91SAM9263_AIC_SVR(27)#define AT91SAM9263_AIC_SVR28 AT91SAM9263_AIC_SVR(28)#define AT91SAM9263_AIC_SVR29 AT91SAM9263_AIC_SVR(29)#define AT91SAM9263_AIC_SVR30 AT91SAM9263_AIC_SVR(30)#define AT91SAM9263_AIC_SVR31 AT91SAM9263_AIC_SVR(31)#define AT91SAM9263_AIC_IVR 0x100#define AT91SAM9263_AIC_FVR 0x104#define AT91SAM9263_AIC_ISR 0x108#define AT91SAM9263_AIC_IPR 0x10c#define AT91SAM9263_AIC_IMR 0x110#define AT91SAM9263_AIC_CISR 0x114#define AT91SAM9263_AIC_IECR 0x120#define AT91SAM9263_AIC_IDCR 0x124#define AT91SAM9263_AIC_ICCR 0x128#define AT91SAM9263_AIC_ISCR 0x12c#define AT91SAM9263_AIC_EOICR 0x130#define AT91SAM9263_AIC_SPU 0x134#define AT91SAM9263_AIC_DCR 0x138#define AT91SAM9263_AIC_FFER 0x140#define AT91SAM9263_AIC_FFDR 0x144#define AT91SAM9263_AIC_FFSR 0x148 /* Parallel Input/Output (PIO) Controller */#define AT91SAM9263_PIO_SIZE 0x200#define AT91SAM9263_PIO_PER 0x00#define AT91SAM9263_PIO_PDR 0x04#define AT91SAM9263_PIO_PSR 0x08#define AT91SAM9263_PIO_OER 0x10#define AT91SAM9263_PIO_ODR 0x14#define AT91SAM9263_PIO_OSR 0x18#define AT91SAM9263_PIO_IFER 0x20#define AT91SAM9263_PIO_IFDR 0x24#define AT91SAM9263_PIO_IFSR 0x28#define AT91SAM9263_PIO_SODR 0x30#define AT91SAM9263_PIO_CODR 0x34#define AT91SAM9263_PIO_ODSR 0x38#define AT91SAM9263_PIO_PDSR 0x3c#define AT91SAM9263_PIO_IER 0x40#define AT91SAM9263_PIO_IDR 0x44#define AT91SAM9263_PIO_IMR 0x48#define AT91SAM9263_PIO_ISR 0x4c#define AT91SAM9263_PIO_MDER 0x50#define AT91SAM9263_PIO_MDDR 0x54#define AT91SAM9263_PIO_MDSR 0x58#define AT91SAM9263_PIO_PUDR 0x60#define AT91SAM9263_PIO_PUER 0x64#define AT91SAM9263_PIO_PUSR 0x68#define AT91SAM9263_PIO_ASR 0x70#define AT91SAM9263_PIO_BSR 0x74#define AT91SAM9263_PIO_ABSR 0x78#define AT91SAM9263_PIO_OWER 0xa0#define AT91SAM9263_PIO_OWDR 0xa4#define AT91SAM9263_PIO_OWSR 0xa8 /* Power Management Controller (PMC) */#define AT91SAM9263_PMC_SIZE 0x84#define AT91SAM9263_PMC_SCER 0x00#define AT91SAM9263_PMC_SCDR 0x04#define AT91SAM9263_PMC_SCSR 0x08#define AT91SAM9263_PMC_PCER 0x10#define AT91SAM9263_PMC_PCDR 0x14#define AT91SAM9263_PMC_PCSR 0x18#define AT91SAM9263_PMC_MOR 0x20#define AT91SAM9263_PMC_MCFR 0x24#define AT91SAM9263_PMC_PLLAR 0x28#define AT91SAM9263_PMC_PLLBR 0x2c#define AT91SAM9263_PMC_MCKR 0x30#define AT91SAM9263_PMC_PCK0 0x40#define AT91SAM9263_PMC_PCK1 0x44#define AT91SAM9263_PMC_IER 0x60#define AT91SAM9263_PMC_IDR 0x64#define AT91SAM9263_PMC_SR 0x68#define AT91SAM9263_PMC_IMR 0x6c#define AT91SAM9263_PMC_PLLICPR 0x80 /* Reset Controller (RSTC) */#define AT91SAM9263_RSTC_SIZE 0x0C#define AT91SAM9263_RSTC_CR 0x00#define AT91SAM9263_RSTC_MR 0x04#define AT91SAM9263_RSTC_SR 0x08 /* Shutdown Controller (SHDWC) */#define AT91SAM9263_SHDWC_SIZE 0x0c#define AT91SAM9263_SHDWC_CR 0x00#define AT91SAM9263_SHDWC_MR 0x04#define AT91SAM9263_SHDWC_SR 0x08 /* Real-time Timer(RTT) */#define AT91SAM9263_RTT_SIZE 0x10#define AT91SAM9263_RTT_MR 0x00#define AT91SAM9263_RTT_AR 0x04#define AT91SAM9263_RTT_VR 0x08#define AT91SAM9263_RTT_SR 0x0c /* Periodic Interval Timer (PIT) */#define AT91SAM9263_PIT_SIZE 0x10#define AT91SAM9263_PIT_MR 0x00#define AT91SAM9263_PIT_SR 0x04#define AT91SAM9263_PIT_PIVR 0x08#define AT91SAM9263_PIT_PIIR 0x0c /* Watchdog Timer (WDT) */#define AT91SAM9263_WDT_SIZE 0x0c#define AT91SAM9263_WDT_CR 0x00#define AT91SAM9263_WDT_MR 0x04#define AT91SAM9263_WDT_SR 0x08 /* * System Controller Register's bit Definition. */ /* (DBGU) */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -